SPSB100 datasheet(23/213 Pages) STMICROELECTRONICS

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3.6.1

State machine without fault transitions

Figure 12. State machine without fault transitions

SPI

cmd

“DO_POWER_CYCLE

” @

state

Power

OFF

START -UP

state

Execute

Power-Up

sequence

Finished OK

any

STATE

DEEP-SLEEP

state

INIT

state

SPSB100

unpowered

Wake-up event

REC-1

state

SPI cmd “DO_POWER_CYCLE”

Execute

Power-Down

sequence

REC-2

state

Execute

Power-Down

sequence

SPI cmd “DO_POWER_DOWN”

SPI cmd “DO_POWER_CYCLE”

SPI cmd “DO_POWER_DOWN”

(WD LOW trigger OK*) & (all flag cleared)

ACTIVE

state

WD trigger OK*

LOW-POWER

mode

FULL-POWER

mode

SPI cmd

WD trigger OK*

START -SM

POR OK

> V

PORVS_R

VVS < VPORVS_F

VFBB_OK_R < VFBB < VFBB_OV

* when LOW_SET = 1111, watchdog service is disabled

Until the voltage on VS pin reaches VPORVS_R for the first time the device is in POWER-OFF state, after that the

device transits to START-UP state where internal power supplies are established. Then core logic reset is

released and START-SM state is reached where oscillators start and NVM is read and checked.

Refer to the Section 3.8: User's NVM modification procedure for details of USER-NVM space programming.

After startup completion the device reaches INIT state where digital BIST is run, and when the FBB voltage

reaches VFBB_OK_R the device executes a power-up sequence which turns ON all regulators as per application

requirements stored in USER-NVM space. The sequence includes the NRST pin deassertion to high level and at

the same time the start of watchdog long open window. See the power-up sequence description in the

Section 3.7.1: Power-up sequence for details. After the power-up sequence the device enters in RECOVERY-1

state: SPSB100 is waiting that MCU boots up and trigs the watchdog, except if LOW_SET[3:0] = 1111, before

expiration of watchdog long open window timeout. After the valid trig of the watchdog during its long open window

timeout the device reaches ACTIVE state in FULL-POWER mode. In an active state the device is fully controllable

by SPI: the MCU can configure SPSB100 features as per application needs to optimize ECU performances and

global power consumption. In particular some regulators can be switched OFF by SPI and SPSB100 can be set in

LOW-POWER mode to reduce ECU power consumption while delivering the strict minimum power supply and

supervision to the MCU. Later the MCU can reconfigure the SPSB100 in FULL-POWER mode by SPI.

In active state, the MCU can also request a power cycle to SPSB100: a power-down sequence is then executed,

followed by digital BIST in INIT state before executing a power-up sequence. In an ACTIVE state, the MCU can

also request a power down to SPSB100: a power-down sequence is then executed and DEEP-SLEEP state is

reached. It is left upon a wake-up event. Wake-up events sensitivity shall be programmable by SPI in ACTIVE

state and includes cyclic sensing of WU pin with cyclic powering of OUT_HS, edge and level detection on IGN

wake-up frame detection.

3.6.2

State machine focusing on fault transitions

3.6.2.1

NVM faults management

The NVM faults management are explained in the Section 3.8.1: Starts-up with valid NVM data and NVM faults

management.

SPSB100

Functional description

DS14640 - Rev 2

page 23/213

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