MPC8280_07 datasheet(10/1386 Pages) FREESCALE

10 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

4.3.1

Interrupt Controller Registers .................................................................................... 4-17

4.3.1.1

SIU Interrupt Configuration Register (SICR)........................................................ 4-17

4.3.1.2

SIU Interrupt Priority Register (SIPRR)................................................................ 4-18

4.3.1.3

CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L) ............................. 4-19

4.3.1.4

SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L) ................................ 4-21

4.3.1.5

SIU Interrupt Mask Registers (SIMR_H and SIMR_L)........................................ 4-22

4.3.1.6

SIU Interrupt Vector Register (SIVEC) ................................................................. 4-24

4.3.1.7

SIU External Interrupt Control Register (SIEXR)................................................. 4-25

4.3.2

System Configuration and Protection Registers ........................................................ 4-26

4.3.2.1

Bus Configuration Register (BCR)........................................................................ 4-26

4.3.2.2

60x Bus Arbiter Configuration Register (PPC_ACR)........................................... 4-29

4.3.2.3

60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)......................... 4-30

4.3.2.4

Local Bus Arbiter Configuration Register (LCL_ACR) ....................................... 4-31

4.3.2.5

Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL) .............. 4-32

4.3.2.6

SIU Module Configuration Register (SIUMCR)................................................... 4-33

4.3.2.7

Internal Memory Map Register (IMMR)............................................................... 4-36

4.3.2.8

System Protection Control Register (SYPCR) ...................................................... 4-37

4.3.2.9

Software Service Register (SWSR) ....................................................................... 4-38

4.3.2.10

60x Bus Transfer Error Status and Control Register 1 (TESCR1) ........................ 4-39

4.3.2.11

60x Bus Transfer Error Status and Control Register 2 (TESCR2) ........................ 4-41

4.3.2.12

Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)................. 4-42

4.3.2.13

Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)................. 4-43

4.3.2.14

Time Counter Status and Control Register (TMCNTSC)...................................... 4-43

4.3.2.15

Time Counter Register (TMCNT) ......................................................................... 4-44

4.3.2.16

Time Counter Alarm Register (TMCNTAL) ......................................................... 4-45

4.3.3

Periodic Interrupt Registers ....................................................................................... 4-46

4.3.3.1

Periodic Interrupt Status and Control Register (PISCR) ....................................... 4-46

4.3.3.2

Periodic Interrupt Timer Count Register (PITC) ................................................... 4-47

4.3.3.3

Periodic Interrupt Timer Register (PITR).............................................................. 4-48

4.3.4

PCI Control Registers ................................................................................................ 4-48

4.3.4.1

PCI Base Register (PCIBRx)................................................................................. 4-49

4.3.4.2

PCI Mask Register (PCIMSKx) ............................................................................ 4-50

4.4

SIU Pin Multiplexing..................................................................................................... 4-50

Chapter 5

Reset

5.1

Reset Causes .................................................................................................................... 5-1

5.1.1

Reset Actions ............................................................................................................... 5-2

5.1.2

Power-On Reset Flow .................................................................................................. 5-2

5.1.3

HRESET Flow ............................................................................................................. 5-3

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