MPC8280_07 datasheet(72/1386 Pages) FREESCALE

72 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lxxii

Freescale Semiconductor

Tables

Table

Number

Title

Page

Number

15-10

SIx RAM Entries for an IDL Interface ............................................................................... 15-29

15-11

GCI Signals ......................................................................................................................... 15-31

15-12

SIx RAM Entries for a GCI Interface (SCIT Mode) .......................................................... 15-33

16-1

Clock Source Options ........................................................................................................... 16-6

16-2

CMXUAR Field Descriptions............................................................................................... 16-7

16-3

CMXSI1CR Field Descriptions .......................................................................................... 16-12

16-4

CMXSI2CR Field Descriptions .......................................................................................... 16-13

16-5

CMXFCR Field Descriptions.............................................................................................. 16-14

16-6

CMXSCR Field Descriptions.............................................................................................. 16-16

16-7

CMXSMR Field Descriptions............................................................................................. 16-19

17-1

BRGCx Field Descriptions ................................................................................................... 17-3

17-2

BRG External Clock Source Options.................................................................................... 17-4

17-3

Typical Baud Rates for Asynchronous Communication ....................................................... 17-5

18-1

TGCR1 Field Descriptions.................................................................................................... 18-4

18-2

TGCR2 Field Descriptions.................................................................................................... 18-5

18-3

TMR1–TMR4 Field Descriptions ......................................................................................... 18-6

18-4

TER Field Descriptions......................................................................................................... 18-8

19-1

SDSR Field Descriptions ...................................................................................................... 19-3

19-2

PDTEM and LDTEM Field Descriptions ............................................................................. 19-5

19-3

IDMA Transfer Parameters ................................................................................................... 19-7

19-4

IDMAx Parameter RAM..................................................................................................... 19-16

19-5

DCM Field Descriptions ..................................................................................................... 19-18

19-6

IDMA Channel Data Transfer Operation............................................................................ 19-20

19-7

Valid Memory-to-Memory STS/DTS Values...................................................................... 19-21

19-8

Valid STS/DTS Values for Peripherals ............................................................................... 19-21

19-9

IDSR/IDMR Field Descriptions.......................................................................................... 19-23

19-10

IDMA BD Field Descriptions ............................................................................................. 19-24

19-11

IDMA Bus Exceptions ........................................................................................................ 19-27

19-12

Parallel I/O Register Programming—Port C ...................................................................... 19-28

19-13

Parallel I/O Register Programming—Port A ...................................................................... 19-28

19-14

Parallel I/O Register Programming—Port D ...................................................................... 19-29

19-15

Example: Peripheral-to-Memory Mode—IDMA2 ............................................................. 19-29

19-16

Example: Memory-to-Peripheral Fly-By Mode (on 60x)–IDMA3 .................................... 19-30

19-17

Programming Example: Memory-to-Memory (PCI-to-60x)—IDMA1.............................. 19-32

20-1

GSMR_H Field Descriptions ................................................................................................ 20-3

20-2

GSMR_L Field Descriptions ................................................................................................ 20-5

20-3

TODR Field Descriptions ................................................................................................... 20-10

20-4

SCC Parameter RAM Map for All Protocols...................................................................... 20-13

20-5

Parameter RAM—SCC Base Addresses............................................................................. 20-15

20-6

RFCRx /TFCRx Field Descriptions.................................................................................... 20-15

20-7

SCCx Event, Mask, and Status Registers ........................................................................... 20-16

MPC8280 Folha de dados(PDF) 72 Page - Freescale Semiconductor, Inc

MPC8280 Folha de dados(HTML) 72 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL