MPC8280_07 datasheet(60/1386 Pages) FREESCALE

60 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

28-9

SMC UART Event Register (SMCE)/Mask Register (SMCM) ......................................... 28-18

28-10

SMC UART Interrupts Example......................................................................................... 28-19

28-11

Synchronization with SMSYNx.......................................................................................... 28-23

28-12

Synchronization with the TSA ............................................................................................ 28-24

28-13

SMC Transparent RxBD ..................................................................................................... 28-26

28-14

SMC Transparent Event Register (SMCE)/Mask Register (SMCM) ................................. 28-28

28-15

SMC Monitor Channel RxBD............................................................................................. 28-32

28-16

SMC Monitor Channel TxBD............................................................................................. 28-33

28-17

SMC C/I Channel RxBD..................................................................................................... 28-33

28-18

SMC C/I Channel TxBD..................................................................................................... 28-34

28-19

SMC GCI Event Register (SMCE)/Mask Register (SMCM) ............................................. 28-35

29-1

BD Structure for One MCC .................................................................................................. 29-3

29-2

TSTATE High Byte ............................................................................................................... 29-7

29-3

INTMSK Mask Bits .............................................................................................................. 29-8

29-4

Channel Mode Register (CHAMR) ...................................................................................... 29-8

29-5

Rx Internal State (RSTATE) High Byte .............................................................................. 29-10

29-6

Channel Mode Register (CHAMR)—Transparent Mode ................................................... 29-12

29-7

INTMSK Mask Bits ............................................................................................................ 29-15

29-8

Channel Mode Register (CHAMR)—CES Mode............................................................... 29-15

29-9

Extended Channel Mode Register (ECHAMR).................................................................. 29-21

29-10

SS7 Configuration Register (SS7_OPT) ............................................................................. 29-23

29-11

Mask1 Format ..................................................................................................................... 29-25

29-12

Mask2 Format ..................................................................................................................... 29-25

29-13

Super Channel Table Entry ................................................................................................. 29-28

29-14

Transmitter Super Channel Example .................................................................................. 29-30

29-15

Receiver Super Channel with Slot Synchronization Example............................................ 29-31

29-16

Receiver Super Channel without Slot Synchronization Example....................................... 29-32

29-17

SI MCC Configuration Register (MCCF)........................................................................... 29-32

29-18

Interrupt Circular Table....................................................................................................... 29-35

29-19

MCC Event Register (MCCE)/Mask Register (MCCM).................................................... 29-36

29-20

Interrupt Circular Table Entry ............................................................................................. 29-37

29-21

MCC Receive Buffer Descriptor (RxBD)........................................................................... 29-42

29-22

MCC Transmit Buffer Descriptor (TxBD).......................................................................... 29-44

30-1

FCC Block Diagram.............................................................................................................. 30-3

30-2

General FCC Mode Register (GFMR).................................................................................. 30-4

30-3

General FCC Expansion Mode Register (GFEMR) ............................................................. 30-8

30-4

FCC Data Synchronization Register (FDSR) ....................................................................... 30-9

30-5

FCC Transmit-on-Demand Register (FTODR)..................................................................... 30-9

30-6

FCC Memory Structure....................................................................................................... 30-10

30-7

Buffer Descriptor Format.................................................................................................... 30-11

30-8

Function Code Register (FCRx) ......................................................................................... 30-14

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