MPC8280_07 datasheet(21/1386 Pages) FREESCALE

21 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

xxi

Contents

Paragraph

Number

Title

Page

Number

Chapter 12

Secondary (L2) Cache Support

12.1

L2 Cache Configurations ............................................................................................... 12-1

12.1.1

Copy-Back Mode ....................................................................................................... 12-1

12.1.2

Write-Through Mode ................................................................................................. 12-2

12.1.3

ECC/Parity Mode....................................................................................................... 12-4

12.2

L2 Cache Interface Parameters ...................................................................................... 12-6

12.3

System Requirements When Using the L2 Cache Interface.......................................... 12-7

12.4

L2 Cache Operation ....................................................................................................... 12-7

12.5

Timing Example............................................................................................................. 12-7

Chapter 13

IEEE 1149.1 Test Access Port

13.1

Overview........................................................................................................................ 13-1

13.2

TAP Controller............................................................................................................... 13-2

13.3

Boundary Scan Register................................................................................................. 13-3

13.4

Instruction Register........................................................................................................ 13-5

13.5

MPC8280 Restrictions ................................................................................................... 13-7

13.6

Nonscan Chain Operation .............................................................................................. 13-7

Part IV

Communications Processor Module

Chapter 14

Communications Processor Module Overview

14.1

Features .......................................................................................................................... 14-1

14.2

Serial Configurations ..................................................................................................... 14-3

14.3

Communications Processor (CP) ................................................................................... 14-4

14.3.1

CPM Performance Evaluation ................................................................................... 14-4

14.3.2

Features ...................................................................................................................... 14-4

14.3.3

CP Block Diagram ..................................................................................................... 14-5

14.3.4

G2_LE Core Interface................................................................................................ 14-7

14.3.5

Peripheral Interface.................................................................................................... 14-7

14.3.6

Execution from RAM ................................................................................................ 14-8

14.3.7

RISC Controller Configuration Register (RCCR) ..................................................... 14-9

14.3.8

RISC Time-Stamp Control Register (RTSCR) ........................................................ 14-10

14.3.9

RISC Time-Stamp Register (RTSR) ........................................................................ 14-11

14.3.10

RISC Microcode Revision Number......................................................................... 14-11

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