MPC8280_07 datasheet(70/1386 Pages) FREESCALE

70 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lxx

Freescale Semiconductor

Tables

Table

Number

Title

Page

Number

9-63

IMIMR Field Descriptions....................................................................................................9-83

9-64

MUCR Field Descriptions .................................................................................................... 9-85

9-65

QBAR Field Descriptions .....................................................................................................9-85

9-66

DMAMRx Field Descriptions............................................................................................... 9-90

9-67

DMASRx Field Descriptions ................................................................................................ 9-92

9-68

DMACDARx Field Descriptions .......................................................................................... 9-93

9-69

DMASARx Field Descriptions ............................................................................................. 9-93

9-70

DMADARx Field Descriptions............................................................................................. 9-94

9-71

DMABCRx Field Descriptions ............................................................................................. 9-95

9-72

DMANDARx Field Descriptions.......................................................................................... 9-96

9-73

DMA Segment Descriptor Fields.......................................................................................... 9-96

10-1

Dedicated PLL Pins .............................................................................................................. 10-5

10-2

SCCR Field Descriptions ...................................................................................................... 10-6

10-3

SCMR Field Descriptions ..................................................................................................... 10-7

10-4

60x Bus-to-Core Frequency .................................................................................................. 10-8

11-1

Number of PSDVAL Assertions Needed for TA Assertion .................................................11-11

11-2

BADDR Connections.......................................................................................................... 11-12

11-3

60x Bus Memory Controller Registers ............................................................................... 11-12

11-4

BRx Field Descriptions ....................................................................................................... 11-13

11-5

ORx Field Descriptions (SDRAM Mode) .......................................................................... 11-16

11-6

ORx—GPCM Mode Field Descriptions ............................................................................. 11-17

11-7

Option Register (ORx)—UPM Mode ................................................................................. 11-19

11-8

PSDMR Field Descriptions................................................................................................. 11-21

11-9

LSDMR Field Descriptions ................................................................................................ 11-24

11-10

Machine x Mode Registers (MxMR) .................................................................................. 11-27

11-11

MDR Field Descriptions ..................................................................................................... 11-29

11-12

MAR Field Description....................................................................................................... 11-30

11-13

60x Bus-Assigned UPM Refresh Timer (PURT)................................................................ 11-30

11-14

Local Bus-Assigned UPM Refresh Timer (LURT)............................................................. 11-31

11-15

60x Bus-Assigned SDRAM Refresh Timer (PSRT) ........................................................... 11-31

11-16

LSRT Field Descriptions..................................................................................................... 11-32

11-17

MPTPR Field Descriptions ................................................................................................. 11-32

11-18

SDRAM Interface Signals .................................................................................................. 11-33

11-19

SDRAM Interface Commands ............................................................................................ 11-35

11-20

SDRAM Address Multiplexing (A0–A15) ......................................................................... 11-38

11-21

SDRAM Address Multiplexing (A16–A31) ....................................................................... 11-38

11-22

60x Address Bus Partition................................................................................................... 11-49

11-23

SDRAM Device Address Port during activate Command.................................................. 11-49

11-24

SDRAM Device Address Port during read/write Command .............................................. 11-49

11-25

11-26

60x Address Bus Partition................................................................................................... 11-50

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