7.4.2 Layout Example

GND

VOUT

VIN

Input cap

Blue line represents

trace on bottom layer

PFM

PWM

GND

VOUT

Output caps

FB

PVIN

AVIN

VOUT

PG

MODE

EN

SW

Figure 7-13. Layout Example

7.4.3 Thermal Considerations

Restrict the maximum IC junction temperature to 125°C under normal operating conditions. Calculate the

maximum allowable dissipation, PD(max), and keep the actual power dissipation less than or equal to PD(max).

The maximum-power-dissipation limit is determined using Equation 8.

A

D max

JA

125

T

P

R

T

(8)

where

• TA is the maximum ambient temperature for the application

• RθJA is the junction-to-ambient thermal resistance given in Thermal Information.

The TPSM81033 comes in a QFN package. The real junction-to-ambient thermal resistance of the package

greatly depends on the PCB type, layout. Using larger and thicker PCB copper for the power pads (GND, PVIN,

and VOUT) to enhance the thermal performance. Using more vias connects the ground plate on the top layer

and bottom layer around the IC without solder mask also improves the thermal capability.

www.ti.com

TPSM81033

SLVSHL0D – JUNE 2024 – REVISED DECEMBER 2024

Copyright © 2024 Texas Instruments Incorporated

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