6.3 Feature Description

6.3.1 Undervoltage Lockout

The TPSM81033 has a built-in undervoltage lockout (UVLO) circuit to ensure the device working properly. When

the analog input voltage (AVIN) is above the UVLO rising threshold of 1.7V (typical), the TPSM81033 can be

enabled to boost the output voltage. The device is disabled when the falling voltage at the AVIN pin trips the

UVLO falling threshold, which is 1.6V (typical). A hysteresis of 100mV (typical) is added so that the device

cannot be enabled again until the input voltage exceeds 1.7V (typical). This function is implemented to prevent

the device from malfunctioning when the input voltage is between UVLO rising and falling threshold.

6.3.2 Enable and Soft Start

When the input voltage is above the UVLO rising threshold and the EN pin is pulled to a voltage above 1.2V, the

TPSM81033 is enabled and starts up. To minimize the inrush current during start up, the TPSM81033 has a soft

start up function. At the beginning, the TPSM81033 enters pre-charge phase and charges the output capacitors

with a current of approximately 330mA when the output voltage is below 0.4V. To minimize the inrush current

further, the TPSM81033 has a maximum pre-charge current of 900mA (typical). After the output voltage reaches

the input voltage, the TPSM81033 starts switching, and the reference voltage ramps up a 0.8mV/μs. When the

voltage at the EN pin is below 0.4V, the internal enable comparator turns the device into shutdown mode. In the

shutdown mode, the device is entirely turned off. The output is disconnected from input power supply.

6.3.3 Setting the Output Voltage

There are two ways to set the output voltage of the TPSM81033: adjustable or fixed. If the FB is connected to

AVIN, the TPSM81033 works as a fixed 5.0V output voltage version, the TPSM81033 uses the internal resistor

divider.The load regulation performance is optimized with the the internal resistor divider.

The output voltage is also can be set by an external resistor divider (R1, R2 in Figure 7-1). When the output

voltage is regulated, the typical voltage at the FB pin is VREF. Thus the resistor divider is determined by Equation

5.

OUT

REF

V

R1

1

R2

V

§

·

u

¨

¸

©

¹

(1)

where

• VOUT is the regulated output voltage

• VREF is the internal reference voltage at the FB pin

6.3.4 Current Limit Operation

The TPSM81033 uses a valley current limit sensing scheme. Current limit detection occurs during the off-time by

sensing of the voltage drop across the synchronous rectifier.

When the load current is increased such that the inductor current is above the current limit within the whole

switching cycle time, the off-time is increased to allow the inductor current to decrease to this threshold before

the next on-time begins (so called frequency foldback mechanism). When the current limit is reached, the output

voltage decreases during further load increase.

The maximum continuous output current (IOUT(LC)), before entering current limit (CL) operation, can be defined

by Equation 2.

OUT(CL)

LIM

L P P

1

I

1 D

I

I

2

§

·

u

'

¨

¸

©

¹

(2)

where

• D is the duty cycle

• ΔIL(P-P) is the inductor ripple current

TPSM81033

SLVSHL0D – JUNE 2024 – REVISED DECEMBER 2024

www.ti.com

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