The duty cycle can be estimated by Equation 3.

IN

OUT

V

D

1

V

u K

(3)

where

• VOUT is the output voltage of the boost converter

• VIN is the input voltage of the boost converter

• η is the efficiency of the converter, use 90% for most applications

The peak-to-peak inductor ripple current is calculated by Equation 4.

IN

L P P

SW

V

D

I

L

f

u

'

u

(4)

where

• L is the inductance value of the inductor

• fSW is the switching frequency

• D is the duty cycle

• VIN is the input voltage of the boost converter

6.3.5 Pass-Through Operation

When the input voltage is higher than the setting output voltage, the output voltage is higher than the target

regulation voltage, the device works in pass-through mode. When the output voltage is 101% of the setting

target voltage, the TPSM81033 stops switching and fully turns on the high-side PMOS FET. The output voltage

is the input voltage minus the voltage drop across the DCR of the inductor and the RDS(on) of the PMOS FET.

When the output voltage drops below the 97% of the setting target voltage as the input voltage declines or the

load current increases, the TPSM81033 resumes switching again to regulate the output voltage.

6.3.6 Power Good Indicator

The TPSM81033 integrates a power good indicator to simplify sequencing and supervision. The power-good

output consists of an open-drain NMOS, requiring an external pullup resistor connect to a suitable voltage

supply. The PG pin goes high with a typical 1.3ms delay time after VOUT is between 93% (typical) and 107%

(typical) of the target output voltage, the hysterisys windown is about 2.5% (typical). When the output voltage is

out of the target output voltage window, the PG pin immediately goes low with a 33μs deglitch filter delay. This

deglitch filter also prevents any false pulldown of the PGOOD due to transients. When EN is pulled low, the PG

pin is also forced low with a 33μs deglitch filter delay. If not used, the PG pin can be left floating or connected to

GND.

6.3.7 Implement Output Discharge by PG function

The purpose of the output discharge function is to ensure a defined down-ramp of the output voltage and to let

the output voltage close to 0V quickly when the device is being disabled. TPSM81033 can implement output

discharge function by PG function that requires a RDummy resistor connected between PG pin and Vout pin. PG

is an open drain NMOS architecture with up to 50mA current capability, the PG pin becomes logic high when the

output voltage reaches the target value, so the dummy load resistor does not lead any power loss during normal

operation. When the EN pin gets low, the TPSM81033 is disabled and meanwhile the PG pin gets low with a

typical 33μs glitch time (tglitch). With PG pin keeps low, the RDummy works as a dummy load to discharge output

voltage. Changing RDummy can adjust the output discharge rate.

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TPSM81033

SLVSHL0D – JUNE 2024 – REVISED DECEMBER 2024

Copyright © 2024 Texas Instruments Incorporated

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