7.2.2 Detailed Design Procedure

7.2.2.1 Setting the Output Voltage

TPSM81033 support the fixed 5V output voltage when FB is connected to AVIN, which can provide better load

regulation performance.

For other output voltage, the output voltage is set by an external resistor divider (R1, R2 in Figure 7-2). When the

output voltage is regulated, the typical voltage at the FB pin is VREF. Thus the resistor divider is determined by

Equation 5.

OUT

REF

V

R1

1

R2

V

§

·

u

¨

¸

©

¹

(5)

where

• VOUT is the regulated output voltage

• VREF is the internal reference voltage at the FB pin

For the best accuracy, keep R2 smaller than 300kΩ to ensure the current flowing through R2 is at least 100

times larger than the FB pin leakage current. Changing R2 towards a lower value increases the immunity against

noise injection. Changing the R2 towards a higher value reduces the quiescent current for achieving highest

efficiency at low load currents.

PVIN

EN

VOUT

FB

GND

OFF

ON

C1

C2

MODE

PFM

PWM

PG

R1

R2

R3

TPSM81033

SW

AVIN

2pcs 22 F(0603)

22 F(0603)

3.3V

Figure 7-2. Coin Battery to 3.3V Boost Converter

7.2.2.2 Output Capacitor Selection

The output capacitor is mainly selected to meet the requirements for output ripple and loop stability. The ripple

voltage is related to capacitor capacitance and its equivalent series resistance (ESR). Assuming a ceramic

capacitor with zero ESR, the minimum capacitance needed for a given ripple voltage can be calculated by

Equation 6.

OUT

MAX

OUT

SW

RIPPLE

I

D

C

f

V

u

u

(6)

where

• DMAX is the maximum switching duty cycle

• VRIPPLE is the peak-to-peak output ripple voltage

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TPSM81033

SLVSHL0D – JUNE 2024 – REVISED DECEMBER 2024

Copyright © 2024 Texas Instruments Incorporated

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