ATXP032 datasheet(21/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

Read Commands

8.1

Read Array (0Bh and 03h)

The Read Array command can be used to sequentially read a continuous stream of data from the device by simply

providing the clock signal once the initial starting address is specified. The device incorporates an internal address

counter that automatically increments every clock cycle.

Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each opcode depends on the

maximum clock frequency that will be used to read data from the device and the mode it operates in. The 0Bh

opcode can be used for any mode at any clock frequency up to the maximum specified by f

CLK. The 03h opcode

can only be used in SPI mode, and can be used for lower frequency read operations up to the maximum specified

by f

RDLF. To be compatible with older host controllers, the 03h opcode is using 3 address bytes instead of 4. This

allows the host controller to read data from the Flash memory without prior knowledge about what type of Flash

device it is connected to.

To perform the read array operation with 3-byte addressing using the 03h command, the CS pin must first be

asserted and the 03h command clocked into the device. After the command has been clocked in, the 3 address

bytes must be clocked in to specify the starting address location of the first byte to read within the memory array.

To perform the fast read array operation with 4-byte addressing using the 0Bh command, the CS pin must first be

asserted and the command 0Bh clocked into the device. After the command has been clocked in, the 4 address

bytes must be clocked in to specify the starting address location of the first byte to be read within the memory

array. After the command, one or more additional dummy bytes need to be clocked into the device. For the SPI

mode, one dummy byte is used. For octal mode, 8 or more dummy cycles are used as shown in Table 7-1 and

Table 12-8. Note that the table refers to full clock cycles, also for DDR modes. Half cycles are not used for dummy

cycles, the settings are a multiple of 2 full cycles.

Table 7-3.

Command Listing 3 — Commands Only Used in Octal Mode (8-8-8)

Command

Maximum

Clock

Frequency

(MHz)

Address

Bytes

Dummy

Cycles

Data

Bytes

Section Link

Octal Mode

Read Commands

Burst Read with Wrap

0Ch

0000 1100

133(1)

8+ (1)

8.2

Miscellaneous Commands

Echo

AAh

1010 1010

150

1 Value

Byte

4 (2)

13.12

Echo with Inversion

A5h

1010 0101

150

1 Value

Byte

4(2)

13.11

Return to Standard SPI Mode

FFh

1111 1111

150

13.15

For more information, refer to Table 11-8, Dummy Clock cycles and Maximum Operating Frequency.

Octal DDR mode adds an additional 1/2 dummy cycle to align the first byte of data to the rising edge of SCK/DS.

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