ATXP032 datasheet(13/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

Figure 6-1.

SPI Mode 0 and 3

6.2

Octal Mode

The ATXP032 features an octal mode to further improve throughput. This allows the command byte to be clocked

in only 1 clock cycle, and for every clock cycle thereafter, eight address bits can be clocked into the device or eight

bits of data can be clocked into or out of the device. Between the address bits and data bits, 4 (or more) dummy

cycles are required as shown in Figures 6-3 and 6-5. An additional half dummy cycle is required for octal DDR as

described in Figure 6-5. The number of dummy cycles required for each command is described in Tables 7-1 and

7-3, and in the individual command descriptions. For octal mode, only SPI mode 0 is supported.

The ATXP032 supports both Single Data Rate (SDR) and Dual Data Rate (DDR) operations in octal mode. See

Section 6.3 for details about DDR mode.

The octal mode is an (8-8-8) mode, using I/O

7-0 for command, address and data. It does require a mode change,

once in this mode the device expects all commands to use this mode. standard SPI mode and octal mode are

exclusive. Only one mode can be active at any given time.

Enter Octal Mode (E8h) and Return to Standard SPI Mode (FFh) commands are used to switch between these two

modes. Upon power-up the default state of the device is standard SPI mode. To enable octal mode, the volatile

Octal Mode Enable (OME) bit in Status/Control register byte 2 is required to be set to 1. The Write Status / Control

The device remains in the same mode while in deep power-down, while it will always wake up in SPI mode when

coming out of ultra-deep power-down. Note that when using the Auto Ultra-Deep Power-Down Mode after a

Program or Erase Operation command, the device switches from octal mode to standard SPI mode after the

program/erase operation has been received. (t

AUDPD after CS goes high.)

Note: If octal mode is enabled by mistake in a system that does not use this mode, the device can be brought back

to standard SPI mode by power cycling the device or by using the JEDEC Hardware Reset command described in

Section 13.9.

6.2.1

Octal Interface Communication Lines

The octal interface has eleven communication lines, as shown in Figure 6-2:

CHIP SELECT (CS): A host-to-device signal. CS operates in push-pull mode. Asserting the CS pin selects the

device. When the CS pin is deasserted, the device is deselected and normally be placed in standby mode

(not deep power-down mode), and the output pins will be in a high-impedance state. When the device is

deselected, data is not accepted on the I/O pins.

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is

required to end an operation. When ending an internally self-timed operation such as a program or erase

cycle, the device does not enter the standby mode until the completion of the operation.

SCK: This is a host-to-device signal. SCK operates in push-pull mode.

MSB

LSB

MSB

LSB

SCK

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