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ATXP032

DS-ATXP032–114I–4-2020

Figure 12-3. Read Status/Control Registers in Octal Mode — DDR

12.6

Read Status Register Byte 1 (05h)

Status/Control Register Byte 1 can be read to determine the device's ready/busy status, as well as the status of

many other functions such as Hardware Locking and Software Protection. Status/Control Register Byte 1 can be

read at any time, including during an internally self-timed program or erase operation.

To read Status/Control Register Byte 1, the CS pin must first be asserted and the 05h command must be clocked

into the device. In Octal mode, 4 dummy cycles have to be clocked into the device. After the command and dummy

cycles have been clocked in, the device begins outputting Status/Control register data on the I/O pins during every

subsequent clock cycle. After the last bit (0) of Status/Control Register Byte 1 has been clocked out, the sequence

repeats itself, starting again with bit 7 of Status/Control Register Byte 1, as long as the CS pin remains asserted

and the clock pin is being pulsed. The data in the Status/Control register is constantly being updated, so each

repeating sequence may output new data.

Deasserting the CS pin terminates the Read Status Register Byte 1 (05h) operation and put the I/O pins into a

high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be

read.

12.6.1 Reading Status Register Byte 1 while in Deep Power-Down

The Read Status Register Byte 1 (05h) command also works while in Deep Power-Down. The DPDS bit in

Status/Control register 1 reads as 1 in this case, while the RDY/BSY and the UDPDS bits reads as 0. This

indicates that the device is in deep power-down.

12.6.2 Reading Status Register Byte 1 while in Ultra-Deep Power-Down

In ultra-deep power-down mode, the Read Status Register Byte 1 (05h) command is only supported in standard

SPI mode. All bits are read as 1 in this mode. Specifically, the UDPDS bit reads as 1 in this mode, and only in this

mode, and can therefore be used as a clear indication that the device is in ultra-deep power-down.

Output

Data

Byte1 Byte2

3 Dummy Cycles

1/2 Dummy Cycle

for Octal DTR Alignment

Address

Bits A

-A

65h

Opcode

I/O7-0

SCK

DDR

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