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ATXP032

DS-ATXP032–114I–4-2020

Figure 12-15. Write Status Register Byte 2 in Octal Mode — DDR

12.10 Active Status Interrupt (25h)

To simplify the readout of the RDY/BSY bit, the Active Status Interrupt command (25h) may be used. It is then not

necessary to continuously read the Status/Control register, it is sufficient to monitor the value of the SO line. If the

SO line is connected to an interrupt line on the host controller, the host controller may be in sleep mode until the

SO line indicates that the ATXP032 is ready for the next command.

The RDY/BSY bit can be read at any time, including during an internally self-timed program or erase operation.

To enable the Active Status Interrupt command, the CS pin must first be asserted and the command of 25h must

be clocked into the device. For SPI Mode 3, at least one dummy bit has to be clocked into the device after the last

bit of the command has been clocked in. (In most cases, this is most easily done by sending a dummy byte to the

device.) The value of the SI line after the command is clocked in is of no significance to the operation. For SPI

Mode 0, this dummy bit (dummy byte) is not required. For octal mode, 4 dummy cycles are required.

The value of RDY/BSY is then output on the SO line, and is continuously updated by the device for as long as the

CS pin remains asserted. All other output pins remain in a high-impedance state.

Additional clocks on the SCK pin are not required. If the RDY/BSY bit changes from 1 to 0 while the CS pin is

asserted, the SO line changes from 1 to 0. The RDY/BSY bit cannot change from 0 to 1 during an operation, so if

the SO line already is 0, it will not change.

Deasserting the CS pin terminates the active status interrupt operation and put the SO pin into a high-impedance

state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

Note: When operating in octal DDR mode at high speed, it is recommended to have the interrupt signal connected

to the SO line internally in the host controller. Connecting an external interrupt pin to the SO line adds additional

load on that one line, adding a delay on this line compared to the others.

Note: The Active Status Interrupt command is intended to be used when the host controller is not actively reading

from the device. When the host controller is actively reading from the device, it can read the RDY/BSY bit by polling

Status/Control Register Byte 1 from time to time.

Input

Data

Byte

31h

Opcode

I/O7-0

SCK

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