ATXP032 datasheet(87/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

The reset sequence does not use the SCK pin. The SCK pin has to be held low (mode 0) or high (mode 3) through

the entire reset sequence. This prevents any confusion with a command, as no command bits are transferred

(clocked).

A reset is commanded when the data on the SI pin is 0101 on four consecutive positive edges of the CS pin with no

edge on the SCK pin throughout. This is a sequence where:

is driven active low to select the device.

Clock (SCK) remains stable in either a high or low state.

SI is driven low by the bus master, simultaneously with CS going active low. No SPI bus slave drives SI during CS

low before a transition of SCK i.e.: slave streaming output active is not allowed until after the first edge of SCK.

is driven inactive. The slave captures the state of SI on the rising edge of CS.

The above steps are repeated 4 times, each time alternating the state of SI.

After the fourth CS pulse, the slave triggers its internal reset. SI is low on the first CS, high on the second, low on

the third, high on the fourth. This provides a value of 5h, unlike random noise. Any activity on SCK during this time

will halt the sequence and a Reset will not be generated.

After a JEDEC hardware reset while the device is in UDPD mode, the SRAM buffer is reset to an undefined value.

All volatile Status/Control registers, including the Sector Protection Bits, are reset to their default values, except in

the following case: If the AUDP bit in Status/Control register byte 2 was set prior to the last Program or Erase

command, the device entered the UDPD mode after a Program or Erase command finished, and the JEDEC

hardware reset is used to wake up the device from UDPD mode, then the EPE bit is not reset. In this case the EPE

bit still shows the correct status after the latest Program or Erase command. All non-volatile Status/Control

registers keep the value they had prior to reset.

After a JEDEC hardware reset while the device is in any other mode than UDPD mode, the SRAM buffer keeps the

values it had prior to reset, with the following exception: If the reset sequence is initiated during an update of the

SRAM buffer, the contents of the SRAM buffer may be corrupted. All volatile Status/Control registers, including the

sector protection bits, are reset to their default values. All non-volatile Status/Control registers keep the value they

had prior to reset, with the following exception: If the reset sequence is initiated during a write to a non-volatile

Status/Control register, the value of that register may be corrupted.

The device always reverts back to standard SPI mode after JEDEC hardware reset.

Figure 13-14 below illustrates the timing for the JEDEC hardware reset operation.

Figure 13-14. JEDEC Standard Hardware Reset

SCK

Internal Reset

mode 3

mode 0

XUDPD

Device is ready

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