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AD6688 Folha de dados(PDF) 107 Page - Analog Devices

Nome de Peças AD6688
Descrição Electrónicos  RF Diversity and 1.2 GHz Bandwidth Observation Receiver
PDF  138 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

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Data Sheet
AD6688
Rev. 0 | Page 107 of 138
Addr.
Name
Bit(s) Bit Name
Setting
Description
Reset
Access
0x0350 DDC2 control
7
DDC2 mixer select
0x0
R/W
0
Real mixer (I and Q inputs must be from the same real channel).
1
Complex mixer (I and Q must be from separate, real and
imaginary quadrature ADC receive channels; analog
demodulator).
6
DDC2 gain select
Gain can be used to compensates for the 6 dB loss associated
with mixing an input signal down to baseband and filtering out
its negative component.
0x0
R/W
0
0 dB gain.
1
6 dB gain (multiply by 2).
[5:4] DDC2 IF mode
0x0
R/W
00
Variable IF mode.
01
0 Hz IF mode.
10
fS Hz IF mode.
11
Test mode.
3
DDC2 complex to real
enable
0x0
R/W
0
Complex (I and Q) outputs contain valid data.
1
Real (I) output only. Complex to real enabled. Uses extra fS mixing
to convert to real.
[2:0] DDC2 decimation rate
select
Decimation filter selection.
0x0
R/W
000
HB1 + HB2 filter selection: decimate by 2 (complex to real
enabled), or decimate by 4 (complex to real disabled).
001
HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real
enabled), or decimate by 8 (complex to real disabled).
010
HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex
to real enabled), or decimate by 16 (complex to real disabled).
011
HB1 filter selection: decimate by 1 (complex to real enabled), or
decimate by 2 (complex to real disabled).
100
HB1 + TB2 filter selection: decimate by 3 (complex to real
enabled), or decimate by 6 (complex to real disabled).
101
HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real
enabled), or decimate by 12 (complex to real disabled).
110
HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex
to real enabled), or decimate by 24 (complex to real disabled).
111
Decimation determined by Register 0x0351, Bits[7:4].
0x0351 DDC2 input
select
[7:4] DDC2 decimation rate
select
Only valid when Register 0x0310, Bits[2:0] = 3'b111
0x0
R/W
0
TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48
(complex to real disabled), or decimate by 24 (complex to real
enabled)
10
FB2 + HB1 filter selection: decimate by 10 (complex to real
disabled), or decimate by 5 (complex to real enabled)
11
FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real
disabled), or decimate by 10 (complex to real enabled)
100
FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex
to real disabled), or decimate by 20 (complex to real enabled)
3
Reserved
Reserved.
0x0
R
2
DDC2 Q input select
0x0
R/W
0
Channel A.
1
Channel B.
1
Reserved
Reserved.
0x0
R
0
DDC2 I input select
0x0
R/W
0
Channel A.
1
Channel B.



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