AD6688 datasheet(74/138 Pages) AD

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AD6688

Data Sheet

Rev. 0 | Page 74 of 138

SETTING UP THE AD6688 DIGITAL INTERFACE

To ensure proper operation of the AD6688 at start-up, some SPI

writes are needed to initialize the link. Additionally, these

registers must be written every time the ADC is reset. Any one

of the following resets warrants the initialization routine for the

digital interface:

•

Hard reset, as in power-up.

•

Power-up using the PDWN pin.

•

Power-up using the SPI (Register 0x0002, Bits[1:0]).

•

SPI soft reset (Register 0x0000 = 0x81).

•

Datapath soft reset (Register 0x0001 = 0x02).

•

JESD204B link power cycle (Register 0x0571 = 0x15, then

0x14).

The initialization SPI writes are as shown in Table 32.

Table 32. AD6688 JESD204B Initialization

Value

Comment

0x1228

0x4F

Reset JESD204B start-up circuit

0x1228

0x0F

JESD204B start-up circuit in normal operation

0x1222

0x00

JESD204B PLL force normal operation

0x1222

0x04

Reset JESD204B PLL calibration

0x1222

0x00

JESD204B PLL normal operation

0x1262

0x08

Clear loss of lock bit

0x1262

0x00

Loss of lock bit normal operation

The AD6688 has one JESD204B link. The serial outputs

(SERDOUT0± to SERDOUT7±) are considered to be part of

one JESD204B link. The basic parameters that determine the

link setup are

•

Number of lanes per link (L)

•

Number of converters per link (M)

•

Number of octets per frame (F)

If the internal DDCs are used for on-chip digital processing, M

represents the number of virtual converters. The virtual

converter mapping setup is shown in Figure 64.

The maximum lane rate allowed by the AD6688 is 16 Gbps. The

lane rate is related to the JESD204B parameters using the

following equation:

Rate

Lane

OUT













where

Ratio

Decimation

CLOCK

ADC

OUT

The decimation ratio (DCM) is the parameter programmed in

Use the following steps to configure the output:

1. Power down the link.

2. Select the JESD204B link configuration options.

3. Configure the detailed options.

4. Set output lane mapping (optional).

5. Set additional driver configuration options (optional).

6. Power up the link.

7. Initialize the JESD204B link by issuing the commands in

Table 32.

Table 33 and Table 34 show the JESD204B output configurations

supported for both N΄ = 16 and N΄ = 8 for a given number of

virtual converters. Take care to ensure that the serial lane rate

for a given configuration is within the supported range of

1.6875 Gbps to 16 Gbps.

See the Example: ADC with DDC Option (Two ADCs Plus Two

DDCs section for an example describing which JESD204B

transport layer settings are valid for a given chip mode.

Table 33. JESD204B Output Configurations for N΄ = 161

No. of

Virtual

Converters

Supported

(Same Value

as M)

JESD204B

Serial

Line

Rate2

Supported

Decimation

Rates for

Lane Rate =

1.7 Gbps to

3.4 Gbps

Supported

Decimation

Rates for

Lane Rate =

3.4 Gbps to

6.8 Gbps

Supported

Decimation

Rates for

Lane Rate =

6.8 Gbps to

13.5 Gbps

Supported

Decimation

Rates for

Lane Rate =

13.5 Gbps to

15.5 Gbps

JESD204B Transport Layer Settings3

20 × fOUT

2, 4, 5, 6, 8, 10,

12, 20, 24

1, 2, 3, 4, 5, 6, 8,

10, 12

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

8 to

0 to

See

Note 4

20 × fOUT

2, 4, 5, 6, 8, 10,

12, 20, 24

1, 2, 3, 4, 5, 6, 8,

10, 12

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

8 to

0 to

See

Note 4

10 × fOUT

1, 2, 3, 4, 5, 6, 8,

10, 12

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

8 to

0 to

See

Note 4

10 × fOUT

1, 2, 3, 4, 5, 6, 8,

10, 12

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

8 to

0 to

See

Note 4

5 × fOUT

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

8 to

0 to

See

Note 4

5 × fOUT

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

8 to

0 to

See

Note 4

2.5 × fOUT

1, 2, 3, 4

1, 2

8 to

0 to

See

Note 4

2.5 × fOUT

1, 2, 3, 4

1, 2

8 to

0 to

See

Note 4

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