AD6688 datasheet(94/138 Pages) AD

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AD6688

Data Sheet

Rev. 0 | Page 94 of 138

MEMORY MAP REGISTER DETAILS

All address locations that are not included in Table 46 to Table 53 are not currently supported for this device and must not be written.

Analog Devices SPI Registers

Table 46.

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset Access

0x0000 SPI Configuration A 7

Soft reset mirror

(self clearing)

Whenever a soft reset is issued, the user must wait 5 ms before

writing to any other register. This provides sufficient time for

the boot loader to complete.

0x0

R/WC

Do nothing.

Reset the SPI and registers (self clearing).

LSB first mirror

0x0

R/W

Least significant bit shifted first for all SPI operations.

Most significant bit shifted first for all SPI operations.

Address ascension mirror

0x0

R/W

Multibyte SPI operations cause addresses to auto-decrement.

Multibyte SPI operations cause addresses to auto-increment.

[4:3] Reserved

Reserved.

0x0

Address ascension

0x0

R/W

Multibyte SPI operations cause addresses to auto-decrement.

Multibyte SPI operations cause addresses to auto-increment.

LSB first

0x0

R/W

Least significant bit shifted first for all SPI operations.

Most significant bit shifted first for all SPI operations.

Soft reset

(self clearing)

Whenever a soft reset is issued, the user must wait 5 ms before

writing to any other register. This provides sufficient time for

the boot loader to complete.

0x0

R/WC

Do nothing.

Reset the SPI and registers (self clearing).

0x0001 SPI Configuration B [7:2] Reserved

Reserved.

0x0

Datapath soft reset

(self clearing)

0x0

R/WC

Normal operation.

Datapath soft reset (self clearing).

Reserved

Reserved.

0x0

0x0002 Chip configuration

(local)

[7:2] Reserved

Reserved.

0x0

[1:0] Channel power mode

Channel power modes.

0x0

R/W

Normal mode (power-up).

Standby mode; digital datapath clocks disabled; JESD204B

interface enabled.

Power-down mode; digital datapath clocks disabled; digital

datapath held in reset; JESD204B interface disabled.

0x0003 Chip type

[7:0] Chip type

Chip type.

0x03

0x3

High speed ADC.

0x0004 Chip ID LSB

[7:0] Chip ID LSB[7:0]

Chip ID.

0xE2

0xE1

AD6688

0x0005 Chip ID MSB

[7:0] Chip ID MSB[15:8]

Chip ID.

0x0

0x0006 Chip grade

[7:4] Chip speed grade

0x0

Chip speed grade.

0x0

[3:0] Reserved

Reserved.

0x0

0x0008 Device index

[7:2] Reserved

Reserved.

0x0

Channel B

0x1

R/W

ADC Core B does not receive the next SPI command.

ADC Core B receives the next SPI command.

Channel A

0x1

R/W

ADC Core A does not receive the next SPI command.

ADC Core A receives the next SPI command.

0x000A Scratch pad

[7:0] Scratch pad

Chip scratch pad register. This register is used to provide a

consistent memory location for software debug.

0x0

R/W

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