AD6688 datasheet(10/138 Pages) AD

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AD6688

Data Sheet

Rev. 0 | Page 10 of 138

SWITCHING SPECIFICATIONS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,

SPIVDD = 1.9 V, sampling rate = 3000 MHz, 1.7 V p-p full-scale differential input, AIN = −2.0 dBFS, L = 8, M = 2, F = 1, −10°C ≤ TJ ≤ +120°C1,

unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C).

Table 4.

Parameter

Min

Typ

Max

Unit

CLOCK

Clock Rate (at CLK+/CLK− Pins)

GHz

Sample Rate2

2500

3000

3100

MSPS

Clock Pulse Width High

161.29

166.67

192.31

Clock Pulse Width Low

161.29

166.67

192.31

OUTPUT PARAMETERS

Unit Interval (UI)3

62.5

66.67

592.6

Rise Time (tR) (20% to 80% into 100 Ω Load)

Fall Time (tF) (20% to 80% into 100 Ω Load)

Phase-Locked Loop (PLL) Lock Time

Data Rate per Channel (NRZ)4

1.6875

Gbps

LATENCY5

Pipeline Latency

Clock cycles

Fast Detect Latency

Clock cycles

WAKE-UP TIME

Standby

400

µs

Power-Down

NCO CHANNEL SELCTION TO OUTPUT

Clock cycles

APERTURE

Aperture Delay (tA)

250

Aperture Uncertainty (Jitter, tJ)

fs rms

Out of Range Recovery Time

Clock cycles

Junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature range of −40°C to+85°C.

The maximum sample rate is the clock rate after the divider.

Baud rate = 1/UI. A subset of this range can be supported.

Default L = 8. This number can be changed based on the sample rate and decimation ratio.

No DDCs used. L = 8, M = 2, F = 1.

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