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AD6688 Folha de dados(PDF) 75 Page - Analog Devices

Nome de Peças AD6688
Descrição Electrónicos  RF Diversity and 1.2 GHz Bandwidth Observation Receiver
PDF  138 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD6688 Folha de dados(HTML) 75 Page - Analog Devices

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Data Sheet
AD6688
Rev. 0 | Page 75 of 138
No. of
Virtual
Converters
Supported
(Same Value
as M)
JESD204B
Serial
Line
Rate2
Supported
Decimation
Rates for
Lane Rate =
1.7 Gbps to
3.4 Gbps
Supported
Decimation
Rates for
Lane Rate =
3.4 Gbps to
6.8 Gbps
Supported
Decimation
Rates for
Lane Rate =
6.8 Gbps to
13.5 Gbps
Supported
Decimation
Rates for
Lane Rate =
13.5 Gbps to
15.5 Gbps
JESD204B Transport Layer Settings3
L
M
F
S
HD
N
N'
CS
K
2
40 × fOUT
4, 8, 10, 12, 15,
16, 20, 24, 30,
40, 48
2, 4, 5, 6, 8, 10,
12, 15, 16, 20,
24, 30
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
1
2
4
1
0
8 to
16
16
0 to
3
See
Note 4
2
40 × fOUT
4, 8, 10, 12, 15,
16, 20, 24, 30,
40, 48
2, 4, 5, 6, 8, 10,
12, 15, 16, 20,
24, 30
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
1
2
8
2
0
8 to
16
16
0 to
3
See
Note 4
2
20 × fOUT
2, 4, 5, 6, 8, 10,
12, 15, 16, 20,
24, 30
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
2
2
2
1
0
8 to
16
16
0 to
3
See
Note 4
2
20 × fOUT
2, 4, 5, 6, 8, 10,
12, 15, 16, 20,
24, 30
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
2
2
4
2
0
8 to
16
16
0 to
3
See
Note 4
2
10 × fOUT
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
4
2
1
1
1
8 to
16
16
0 to
3
See
Note 4
2
10 × fOUT
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
4
2
2
2
0
8 to
16
16
0 to
3
See
Note 4
2
5 × fOUT
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
1
8
2
1
2
1
8 to
16
16
0 to
3
See
Note 4
2
5 × fOUT
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
1
8
2
2
4
0
8 to
16
16
0 to
3
See
Note 4
4
80 × fOUT
8, 16, 20, 24, 30,
40, 48
4, 8, 10, 12, 16,
20, 24, 30, 40,
48
2, 4, 6, 8, 10,
12, 16, 20, 24,
30
2, 4, 6, 8, 10, 12,
16
1
4
8
1
0
8 to
16
16
0 to
3
See
Note 4
4
40 × fOUT
4, 8, 10, 12, 15,
16, 20, 24, 30,
40, 48
2, 4, 5, 6, 8, 10,
12, 15, 16, 20,
24, 30
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
2
4
4
1
0
8 to
16
16
0 to
3
See
Note 4
4
40 × fOUT
4, 8, 10, 12, 15,
16, 20, 24, 30,
40, 48
2, 4, 5, 6, 8, 10,
12, 15, 16, 20,
24, 30
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
2
4
8
2
0
8 to
16
16
0 to
3
See
Note 4
4
20 × fOUT
2, 4, 5, 6, 8, 10,
12, 15, 16, 20,
24, 30
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
4
4
2
1
0
8 to
16
16
0 to
3
See
Note 4
4
20 × fOUT
2, 4, 5, 6, 8, 10,
12, 15, 16, 20,
24, 30
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
4
4
4
2
0
8 to
16
16
0 to
3
See
Note 4
4
10 × fOUT
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
8
4
1
1
1
8 to
16
16
0 to
3
See
Note 4
4
10 × fOUT
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
8
4
2
2
0
8 to
16
16
0 to
3
See
Note 4
8
160 × fOUT
16, 40, 48
8, 16, 20, 24,
40, 48
4, 8, 12, 16, 20,
24, 40, 48
4, 8, 12, 16, 20,
24
1
8
16
1
0
8 to
16
16
0 to
3
See
Note 4
8
80 × fOUT
8, 16, 20, 24, 40,
48
4, 8, 10, 12, 16,
20, 24, 40, 48
2, 4, 6, 8, 10,
12, 16, 20, 24
2, 4, 6, 8, 10, 12,
16
2
8
8
1
0
8 to
16
16
0 to
3
See
Note 4
8
40 × fOUT
4, 8, 10, 12, 16,
20, 24, 40, 48
2, 4, 6, 8, 10,
12, 16, 20, 24
2, 4, 6, 8, 10,
12, 16
2, 4, 6, 8
4
8
4
1
0
8 to
16
16
0 to
3
See
Note 4
8
40 × fOUT
4, 8, 10, 12, 16,
20, 24, 40, 48
2, 4, 6, 8, 10,
12, 16, 20, 24
2, 4, 6, 8, 10,
12, 16
2, 4, 6, 8
4
8
8
2
0
8 to
16
16
0 to
3
See
Note 4
8
20 × fOUT
2, 4, 6, 8, 10, 12,
16, 20, 24
2, 4, 6, 8, 10,
12, 16
2, 4, 6, 8
2, 4
8
8
2
1
0
8 to
16
16
0 to
3
See
Note 4
8
20 × fOUT
2, 4, 6, 8, 10, 12,
16, 20, 24
2, 4, 6, 8, 10,
12, 16
2, 4, 6, 8
2, 4
8
8
4
2
0
8 to
16
16
0 to
3
See
Note 4
1
Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.
2
JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter
device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the
virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the
number of frames per multiframe.
3
fADC_CLK is the ADC sample rate; DCM = chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations must be
met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64. When the SLR
is ≤ 15500 Mbps and > 13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set to 0x00. When the SLR is
< 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must be set to 0x50.
4
Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4,
8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.



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