AD6688 datasheet(9/138 Pages) AD

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Data Sheet

AD6688

Rev. 0 | Page 9 of 138

DIGITAL SPECIFICATIONS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,

SPIVDD = 1.9 V, sampling rate = 3000 MHz, 1.7 V p-p full-scale differential input, AIN = −2.0 dBFS, L = 8, M = 2, F = 1, −10°C ≤ TJ ≤ +120°C1,

unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C).

Table 3.

Parameter

Min

Typ

Max

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

LVDS/LVPECL

Differential Input Voltage

300

800

1800

mV p-p

Input Common-Mode Voltage

0.675

Input Resistance (Differential)

106

Input Capacitance

0.9

Differential Input Return Loss at 3 GHz2

−9.4

SYSREF INPUTS (SYSREF+, SYSREF−)

Logic Compliance

LVDS/LVPECL

Differential Input Voltage

400

800

1800

mV p-p

Input Common-Mode Voltage

0.675

2.0

Input Resistance (Differential)

kΩ

Input Capacitance (Differential)

LOGIC INPUT (SDIO, SCLK, CSB, PDWN/STBY, FD_A/GPIO_A0,

FD_B/GPIO_B0, GPIO_A1, GPIO_B1)

Logic Compliance

CMOS

Logic 1 Voltage

0.65 × SPIVDD

Logic 0 Voltage

0.35 × SPIVDD

Input Resistance

kΩ

LOGIC OUTPUT (SDIO, FD_A, FD_B)

Logic Compliance

CMOS

Logic 1 Voltage (IOH = 4 mA)

SPIVDD − 0.45V

Logic 0 Voltage (IOL = 4 mA)

0.45

SYNCIN INPUT (SYNCINB+/SYNCINB−)

Logic Compliance

LVDS/LVPECL

Differential Input Voltage

400

800

1800

mV p-p

Input Common-Mode Voltage

0.675

2.0

Input Resistance (Differential)

kΩ

Input Capacitance

SYNCINB+ INPUT

Logic Compliance

CMOS

Logic 1 Voltage

0.9 × DRVDD1

2 × DRVDD1

Logic 0 Voltage

0.1 × DRVDD1

Input Resistance

2.6

kΩ

DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 7)

Logic Compliance

SST

Differential Output Voltage

360

560

770

mV p-p

Differential Termination Impedance

100

120

Junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature range of −40°C to+85°C.

Reference impedance = 100 Ω.

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