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AD6688 Folha de dados(PDF) 105 Page - Analog Devices

Nome de Peças AD6688
Descrição Electrónicos  RF Diversity and 1.2 GHz Bandwidth Observation Receiver
PDF  138 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD6688 Folha de dados(HTML) 105 Page - Analog Devices

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Data Sheet
AD6688
Rev. 0 | Page 105 of 138
Addr.
Name
Bit(s) Bit Name
Setting
Description
Reset
Access
3
DDC1 complex to real
enable
0x0
R/W
0
Complex (I and Q) outputs contain valid data.
1
Real (I) output only. Complex to real enabled. Uses extra fS mixing
to convert to real.
[2:0] DDC1 decimation rate
select
Decimation filter selection.
0x0
R/W
000
HB1 + HB2 filter selection: decimate by 2 (complex to real
enabled), or decimate by 4 (complex to real disabled).
001
HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real
enabled), or decimate by 8 (complex to real disabled).
010
HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex
to real enabled), or decimate by 16 (complex to real disabled).
011
HB1 filter selection: decimate by 1 (complex to real enabled), or
decimate by 2 (complex to real disabled).
100
HB1 + TB2 filter selection: decimate by 3 (complex to real
enabled), or decimate by 6 (complex to real disabled).
101
HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real
enabled), or decimate by 12 (complex to real disabled).
110
HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex
to real enabled), or decimate by 24 (complex to real disabled).
111
Decimation determined by Register 0x0331, Bits[7:4].
0x0331 DDC1 input
select
[7:4] DDC1 decimation rate
select
Only valid when Register 0x0310, Bits[2:0] = 3'b111.
0x0
R/W
0
TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48
(complex to real disabled), or decimate by 24 (complex to real
enabled).
10
FB2 + HB1 filter selection: decimate by 10 (complex to real
disabled), or decimate by 5 (complex to real enabled).
11
FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real
disabled), or decimate by 10 (complex to real enabled).
100
FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex
to real disabled), or decimate by 20 (complex to real enabled).
111
TB1 filter selection: decimate by 3 (decimate by 1.5 not
supported).
1000
FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not
supported).
1001
HB2 + FB2 + TB1 filter selection: decimate by 30 (decimate by 15
not supported).
3
Reserved
Reserved.
0x0
R
2
DDC1 Q input select
0x1
R/W
0
Channel A.
1
Channel B.
1
Reserved
Reserved.
0x0
R
0
DDC1 I input select
0x1
R/W
0
Channel A.
1
Channel B.
0x0334 DDC1 NCO
control
[7:4] DDC1 NCO channel
select mode
For edge control, the internal counter wraps when the
Register 0x0334, Bits[3:0] value is reached.
0x0
R/W
0
Use Register 0x0314, Bits[3:0].
1
2'b0, GPIO B0, GPIO A0.
10
2'b0, GPIO B1, GPIO A1.
11
2'b00, GPIO A1, GPIO A0.
100
2'b00, GPIO B1, GPIO B0.
101
GPIO B1, GPIO A1, GPIO B0, GPIO A0.
110
GPIO B1, GPIO B0, GPIO A1, GPIO A0.
1000
Increment internal counter when rising edge of the GPIO_A0 pin.
1001
Increment internal counter when rising edge of the GPIO_A1 pin.
1010
Increment internal counter when rising edge of the GPIO_B0 pin.
1011
Increment internal counter when rising edge of the GPIO_B1 pin.



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