 |
Os motores de busca de Datasheet de Componentes eletrônicos |
|
|
Os motores de busca de Datasheet de Componentes eletrônicos |
|
AM652X Folha de dados(PDF) 266 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AM652X Folha de dados(HTML) 266 Page - Texas Instruments |
|
|
266 / 299 page  266 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Detailed Description Copyright © 2017–2018, Texas Instruments Incorporated The GPMC supports the following various access types: • Asynchronous read/write access • Asynchronous read page access (4, 8, and 16 Word16) • Synchronous read/write access • Synchronous read/write burst access without wrap capability (4, 8 and 16 Word16) • Synchronous read/write burst access with wrap capability (4, 8 and 16 Word16) • Address-data-multiplexed (AD) access • Address-address-data (AAD) multiplexed access • Little-endian access only The GPMC can communicate with a wide range of external devices: • External asynchronous or synchronous 8-bit wide memory or device (non burst device) • External asynchronous or synchronous 16-bit wide memory or device • External 16-bit non-multiplexed NOR flash device • External 16-bit address and data multiplexed NOR Flash device • External 8-bit and 16-bit NAND flash device • External 16-bit pseudo-SRAM (pSRAM) device The following features are not supported on this family of devices: • DMA mode is not supported. • WAIT[3:2] are not pinned out. All CS regions must use WAIT0 or WAIT1. • Asynchronous page write mode is not supported. • Multiple write access in asynchronous mode is not supported. • Multiple read is not supported in address/data-multiplexed and AAD-multiplexed modes. For more information, see section General-Purpose Memory Controller (GPMC) in chapter Peripherals of the device TRM. 6.11.14 HYPERBUS The Hyperbus module is a part of the device Flash Subsystem (FSS). The Hyperbus module is low pin count memory interface that provides high read/write performance. The Hyperbus module connects to hyperbus memory (HyperFlash or HyperRAM) and uses simple hyperbus protocol for read and write transactions. There is one Hyperbus module inside the device. The Hyperbus module includes one HyperBus Memory Controller (HBMC). Hyperbus module supports the following features: • Support for Cypress®/Spansion® HyperFlash and HyperRAM • Up to 166 MHz maximum memory bus operation for reads – Support up to 166 MHz dual data rate (333 MBps) flash devices for system requiring rapid boot or instant-on displays – Support up to 333 MBps external pseudo-RAM (HyperRAM) for systems • Low pin count interface with LVCMOS I/O pins that may be muxed with other FSS interfaces (OSPIs) • Two memory chip selects • Linear incrementing mode for reads and writes • Up to 16 outstanding read transactions • Asynchronous bus clock Hyperbus Not Supported Features: • Cache-line wrap and fixed address modes for reads or writes |
|
Ligação URL |
| ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | Link para a ficha técnica | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Portuguese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
