AM652X datasheet(269/299 Pages) TI1

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269

AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

Although intercomponent digital audio interface reception (DIR) mode (this is, S/PDIF stream receiving) is

not natively supported by the MCASP module, a specific TDM mode implementation for the MCASP

receivers allows an easy connection to external DIR components (for example, S/PDIF to I2S format

converters).

The device have integrated three MCASP modules with:

•

MCASP0 supporting up to 16 channels with independent TX/RX clock/sync domain

•

MCASP1 supporting up to 10 channels with independent TX/RX clock/sync domain

•

MCASP2 supporting up to 4 channels with independent TX/RX clock/sync domain

MCASP module includes the following main features:

•

Independent serializer for each AXRx channel of each MCASP module.

•

Clock stop request/acknowledge protocol

•

A single 32-bit buffer per serializer for transmit and receive operations

•

1 x interconnect interface port for CBASS0

•

Two independent clock generator modules for transmit and receive.

–

Clocking flexibility allows the MCASP to receive and transmit at different rates. For example, the

MCASP can receive data at 48 kHz but output up-sampled data at 96 kHz or 192 kHz.

•

MCASP module functional clock can be generated:

–

internally (master mode)

–

supplied over MCASP serial interface (slave mode)

–

has a controllable functional clock divide ratio

•

Independent transmit and receive modules, each includes:

–

Programmable clock and frame sync generator.

–

TDM streams from 2 to 32, and 384 time slots.

–

Support for time slot sizes of 8, 12, 16, 20, 24, 28, and 32 bits.

–

Data formatter for bit manipulation.

•

Glueless connection to audio analog-to-digital converters (ADC), digital-to-analog converters (DAC),

codec, digital audio interface receiver (DIR), and S/PDIF transmit physical layer components.

•

Wide variety of I2S and similar bit-stream format.

•

Integrated digital audio interface transmitter (DIT):

–

S/PDIF, IEC60958-1, AES-3 formats.

–

Enhanced channel status/user data RAM.

•

384-slot TDM with external digital audio interface receiver (DIR) device.

–

For DIR reception, an external DIR receiver integrated circuit should be used with I2S output format

and connected to the MCASP receive section.

•

Support for 2x DMA requests (one per direction):

–

1 level-sensitive transmit direct memory access (DMA) request common for all of the MCASP

serializers

–

1 level-sensitive receive direct memory access (DMA) request common for all of the MCASP

serializers

–

All transmit DMA requests are mapped to the device DMA controllers

•

One transmit interrupt request common for all serializers

•

One receive interrupt request common for all serializers

•

Each of the Rx and Tx interrupts is propagated to different host processors via the device Interrupts

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