AM652X datasheet(270/299 Pages) TI1

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270

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Detailed Description

NOTE

Because a serializer receive and transmit channels data is shared on the same MCASP data

pin, user can choose to have either Tx or Rx function from a serializer, not both at the same

time.

The MCASP module does not support the following features:

•

Muting output (AMUTE)

•

Muting input (AMUTEIN)

For more information, see section Multi-channel Audio Serial Port (McASP) in chapter Peripherals of the

device TRM.

6.11.18 MCRC Controller

VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify

the integrity of a memory system. A signature representing the contents of the memory is obtained when

the contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to

calculate the signature for a set of data and then compare the calculated signature value against a pre-

determined good signature value. MCRC controller provides four channels to perform CRC calculation on

multiple memories in parallel and can be used on any memory system. Channel 1 can also be put into

data trace mode, where MCRC controller compresses each data being read through CPU read data bus.

MCRC has the following features:

•

Four channels to perform background signature verification on any memory subsystem

•

Data compression on 8-, 16-, 32-, and 64-bit data size

•

Maximum-length PSA (Parallel Signature Analysis) register constructed based on 64-bit primitive

polynomial

•

Each channel has a CRC Value Register which contains the pre-determined CRC value

•

Use timed base event trigger from timer to initiate DMA data transfer

•

Programmable 20-bit pattern counter per channel to count the number of data patterns for

compression

•

Three modes of operation:

–

Auto

–

Semi-CPU

–

Full-CPU

•

For each channel, CRC can be performed either by MCRC Controller or by CPU

•

Automatically performs signature verification without CPU intervention in AUTO mode

•

Generates interrupt to CPU in Semi-CPU mode to allow CPU to perform signature verification itself

•

Generates CRC fail interrupt in AUTO mode if signature verification fails

•

Generates Timeout interrupt if CRC is not performed within the time limit

•

Generates DMA request per channel to initiate CRC value transfer

•

An 128-byte block burst address for the PSA register to DMA without constant mode bus attribute

For more information, see section MCRC Controller in chapter Interprocessor Communication of the

device TRM.

6.11.19 MCSPI

The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus.

There are total of eight MCSPI modules in the device.

MCSPI3 and MCSPI4 include internal connectivity to MCSPI modules in the MCU domain, as follows:

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