AM652X datasheet(264/299 Pages) TI1

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264

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

The encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be at

a geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from

the QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line

encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of

166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can

determine the velocity of the motor.

The EQEP module includes the following features:

•

EQEP inputs (A/B/INDEX and STROBE) are available at chip level

•

EQEP phase error output is also available

The following EQEP features are not supported:

•

EQEP quadrature outputs (A and B) are not pinned out

For more information, see section Enhanced Quadrature Encoder Pulse (EQEP) Module in chapter

Peripherals of the device TRM.

6.11.12 GPIO

The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be

configured as either inputs or outputs. When configured as an output, user can write to an internal register

to control the state driven on the output pin. When configured as an input, user can obtain the state of the

input by reading the state of an internal register.

In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in

different interrupt/event generation modes.

The device has three instances of GPIO144 modules. The GPIO pins are grouped into banks (16 pins per

bank), which means that each GPIO module provides up to 144 dedicated general-purpose pins with input

and output capabilities; thus, the general-purpose interface supports up to 432 (3 instances × (9 banks ×

16 pins)) pins. Since WKUP_GPIO0_[56:143], GPIO0_[96:143], and GPIO1_[90:143] are reserved in this

Device, general purpose interface supports up to 242 pins.

Each channel in the GPIO modules has the following features:

•

Supports 9 banks of 16 GPIO signals

•

Supports up to 9 banks of interrupt capable GPIOs

•

Interrupts:

–

Can enable interrupts for each bank of 16 GPIO signals

–

Interrupts can be triggered by rising and/or falling edge (or neither edge = disabled), specified for

each interrupt capable GPIO signal

•

Set/clear functionality:

–

Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO signal(s). This allows

multiple firmware processes to toggle GPIO output signals without critical section protection

(disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to another

process during GPIO programming).

•

Separate Input/Output registers:

–

Output register in addition to set/clear so that if preferred by firmware, some GPIO output signals

can be toggled by direct write to the output register(s).

–

Output register, when read in, reflects output drive status. This, in addition to the input register

reflecting pin status and open-drain I/O cell, allows wired logic be implemented.

GPIO do not support the following features:

GPIO Not Supported Features:

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