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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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AM652X Folha de dados(PDF) 267 Page - Texas Instruments |
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AM652X Folha de dados(HTML) 267 Page - Texas Instruments |
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267 / 299 page  267 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Detailed Description Copyright © 2017–2018, Texas Instruments Incorporated • General Purpose Output register of the HBMC is not used For more information, see section Hyperbus Interface in chapter Peripherals of the device TRM. 6.11.15 I2C The device contains six multimaster inter-integrated circuit (I2C) controllers each of which provides an interface between a local host (LH), such as an Arm and any I2C-bus-compatible device that connects via the I2C serial bus. External components attached to the I2C bus can serially transmit and receive up to 8 bits of data to and from the LH device through the 2-wire I2C interface. Each multimaster I2C module can be configured to act like a slave or master I2C-compatible device. WKUP_I2C0 and MCU_I2C0 controllers have dedicated I2C compliant open drain buffers, and support Fast mode (up to 400 Kbps). I2C0, I2C1, I2C2, and I2C3 controllers are multiplexed with standard LVCMOS I/O and connected to emulate open drain. I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic 1. For the specific I/O timing characteristics of the different I2C instances, see Section 5.11.5.12, I2C. The multimaster I2C module has the following features: • Compliant with Philips I2C-bus specification version 2.1 • Supports a standard mode (up to 100 Kbps) and fast mode (up to 400 Kbps) • 7-bit and 10-bit device addressing modes • General call • Start/Restart/Stop • Multimaster transmitter/slave receiver mode • Multimaster receiver/slave transmitter mode • Built-in configurable FIFOs (8, 16, 32, 64 bytes) for buffered read or write • Module enable/disable capability • Programmable multislave channel (responds to four separate addresses) • Programmable clock generation • 8-bit-wide data access • Designed for low power consumption • Implement Auto Idle mechanism • Implement Idle Request/Idle Acknowledge handshake mechanism • Support for asynchronous wakeup mechanism • Wide interrupt capability I2C Not Supported Features: • Serial Camera Control Bus (SCCB) Protocol • High-Speed (HS) Mode • DMA Mode • Full I2C electrical compliance only for MAIN domain I2C modules For more information, see section Inter-Integrated Circuit (I2C) Interface in chapter Peripherals of the device TRM. 6.11.16 MCAN The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a high level of security. CAN has high immunity to electrical interference and the ability to self-diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire network, which provides for data consistency in every node of the system. |
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