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AM652X Folha de dados(PDF) 262 Page - Texas Instruments

Nome de Peças AM652X
Descrição Electrónicos  Sitara Processors
PDF  299 Pages
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Fabricante Electrônico  TI1 [Texas Instruments]
Página de início  http://www.ti.com
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AM652X Folha de dados(HTML) 262 Page - Texas Instruments

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AM6548, AM6528, AM6546
AM6526, AM6527
SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018
www.ti.com
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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
Dedicated 16-bit time-base counter with period and frequency control
Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations:
Two independent PWM outputs with single-edge operation
Two independent PWM outputs with dual-edge symmetric operation
One independent PWM output with dual-edge asymmetric operation
Asynchronous override control of PWM signals through software
Programmable phase-control support for lag or lead operation relative to other EPWM modules
Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis
Dead-band generation with independent rising and falling edge delay control
Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions
A trip condition can force either high, low, or high-impedance state logic levels at PWM outputs
Allows events to trigger both CPU interrupts and ADC start of conversions
Programmable event prescaling minimizes CPU overhead on interrupts
PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives
High-resolution module with programmable delay line
Programmable on a per PWM period basis
Can be inserted either on the rising edge or falling edge of the PWM pulse or both or not at all.
EHRPWM Not Supported Features:
EPWM digital comparator modules are not supported
For more information, see section Enhanced High Resolution Pulse Width Modulation (EHRPWM) Module
in chapter Peripherals of the device TRM.
6.11.9 ELM
The ELM is used with the GPMC. Syndrome polynomials generated on-the-fly when reading a NAND flash
page and stored in GPMC registers are passed to the ELM. A host processor can then correct the data
block by flipping the bits to which the ELM error-location outputs point.
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction
process is delegated to the memory controller.
The General-Purpose Memory Controller (GPMC) probes data read from an external NAND flash and
uses this to compute checksum-like information, called syndrome polynomials, on a per-block basis. Each
syndrome polynomial gives a status of the read operations for a full block, including 512 bytes of data,
parity bits, and an optional spare-area data field, with a maximum block size of 1023 bytes. Computation
is based on a Bose-Chaudhuri-Hocquenghem (BCH) algorithm. The ELM extracts error addresses from
these syndrome polynomials.
Based on the syndrome polynomial value, the ELM can detect errors, compute the number of errors, and
give the location of each error bit. The actual data is not required to complete the error-correction
algorithm. Errors can be reported anywhere in the NAND flash block, including in the parity bits.
The maximum acceptable number of errors that can be corrected depends on a programmable
configuration parameter. 4-, 8-, and 16-bit error-correction levels are supported. The ELM depends on a
static and fixed definition of the generator polynomial for each error-correction level that corresponds to
the generator polynomials defined in the GPMC (there are three fixed polynomial for the three correction
error levels). A larger number of errors than the programmed error-correction level may be detected, but
the ELM cannot correct them all. The offending block is then tagged as uncorrectable in the associated
computation exit status register. If the computation is successful, that is, if the number of errors detected
does not exceed the maximum value authorized for the chosen correction capability, the exit status
register contains the information on the number of detected errors.



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