AM652X datasheet(265/299 Pages) TI1

265 / 299 page

265

AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

•

The following apply to WKUP_GPIO0:

–

WKUP_GPIO0_[56:143] are not pinned out.

–

Interrupts [56:143] are not pinned out.

–

Bank Interrupts [8:4] are not pinned out.

•

The following apply to GPIO0:

–

GPIO0_[96:143] are not pinned out.

–

Interrupts [96:143] are not pinned out.

–

Bank Interrupts [8:6] are not pinned out.

•

The following apply to GPIO1:

–

GPIO1_[90:143] are not pinned out.

–

Interrupts [90:143] are not pinned out.

–

Bank Interrupts [8:6] are not pinned out.

–

GPI[10,77] buffer is output only.

–

Interrupt [10,77] buffer is output only.

–

GPO[12] buffer is input only.

For more information, see section General-Purpose Interface (GPIO) in chapter Peripherals of the device

TRM.

6.11.13 GPMC

The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with

external memory devices like:

•

Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices

•

Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash

devices

•

NAND flash

•

Pseudo-SRAM devices

The main features of the GPMC are:

•

8- or 16-bit-wide data path to external memory device

•

Supports up to 4 chip select regions of programmable size and programmable base addresses in a

total address space of 1 GB

•

Supports on-the-fly error code detection using the Bose-ChaudhurI-Hocquenghem (BCH) (t = 4, 8, or

16) or Hamming code to improve the reliability of NAND with a minimum effect on software (NAND

flash with 512-byte page size or greater)

•

Fully pipelined operation for optimal memory bandwidth usage

•

The clock to the external memory is provided from GPMC_FICLK divided by 1, 2, 3, or 4

•

Supports programmable autoclock gating when no access is detected

•

Independent and programmable control signal timing parameters for setup and hold time on a per-chip

basis. Parameters are set according to the memory device timing parameters with a timing granularity

of one GPMC_FICLK clock cycle.

•

Flexible internal access time control (wait state) and flexible handshake mode using external WAIT pin

monitoring

•

Support bus keeping

•

Support bus turnaround

•

Prefetch and write posting engine associated with DMA controller at system level to achieve full

performance from the NAND device with minimum effect on NOR/SRAM concurrent access

•

32-bit interconnect slave interface which supports non-wrapping and wrapping burst of up to 16x32

bits.

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