COP8CCR9KMT7 datasheet(53/84 Pages) NSC

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15.0 A/D Converter (Continued)

TABLE 21. A/D Converter Channel Selection when the Multiplexor Output is Enabled

Select Bits

Mode Select

ADMOD = 0

Single Ended

Mode

Mode Select

ADMOD = 1

Differential

Mode

Mux Output

Enabled

ADCH3

ADCH2

ADCH1

ADCH0

Channel No.

Channel Pairs

(+, −)

MUX

00000

0, 1

00011

1, 0

00102

2, 3

00113

3, 2

01004

4, 5

01015

5, 4

01106

6, 7

01117

7, 6

10008

8, 9

10019

9, 8

1010

10, 11

1011

11, 10

1100

Not Used (Note

19)

1101

ADC13 is

Mux Output −

(Note 19)

1110

ADCH14 is

Mux Output

(Note 18)

ADCH14 is

Mux Output +

(Note 18)

1111

ADCH15 is

A/D Input (Note

18)

ADCH15 is

A/D Input (Note

18)

Note 18: This Input Channel Selection should not be used when the Multiplexor Output is enabled.

Note 19: This Input Channel Selection should not be used in Differential Mode when the Multiplexor Output is enabled.

15.1.1.2 Multiplexor Output Select

This 1-bit field allows the output of the A/D multiplexor and

the input to the A/D to be connected directly to external pins.

This allows for an external, common filter/signal conditioning

circuit to be applied to all channels. The output of the exter-

nal conditioning circuit can then be connected directly to the

input of the Sample and Hold input on the A/D Converter.

See Figure 26 for the single ended mode diagram. The

Multiplexor output is connected to ADCH14 and the A/D

input is connected to ADCH15. For Differential mode, the

differential multiplexor outputs are available and should be

converted to a single ended voltage for connection to the A/D

Converter Input. See Figure 27.

The channel assignments for this mode are shown in Table

22.

When using the Mux Output feature, the delay though the

internal multiplexor to the pin, plus the delay of the external

filter circuit, plus the internal delay to the Sample and Hold

will exceed the three clock cycles that’s allowed in the con-

version. This adds the requirement that, whenever the MUX

bit = 1, that the channel selected by ADCH3:0 bits be en-

abled, even when ADBSY = 0, and gated to the mux output

pin. The input path to the A/D converter is also enabled. This

allows the input channel to be selected and settled before

starting a conversion. The sequence to perform conversions

using the Mux Out feature is a multistep process and is listed

below.

Select the desired channel and operating modes and

load them into ENAD without setting ADBSY.

Wait the appropriate time until the analog input has

settled. This will depend on the application and the

response of the external circuit.

Select the same desired channel and operating modes

used in step 1 and load them into ENAD and also set

ADBSY or set ADBSY by using the SBIT instruction.

This will start the conversion.

Poll ADBSY until it is cleared by the hardware. This

indicates the completion of the conversion.

Obtain the results from the result registers.

The port pins used for the multiplexor output must be con-

figured as high impedance inputs. If the port pins are con-

figured as outputs, or as inputs with weak pull-up, there will

be a conflict between the analog signal output and the

digitally driven output.

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