EM260-RTR datasheet(7/50 Pages) SILICONIMAGE

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EM260

Page 7

120-0260-000M Rev 1.1

Top-Level Functional Description

Figure 3 shows a detailed block diagram of the EM260.

Figure 3. EM260 Block Diagram

The radio receiver is a low-IF, super-heterodyne receiver. It utilizes differential signal paths to minimize noise

interference, and its architecture has been chosen to optimize co-existence with other devices within the

2.4GHz band (namely, IEEE 802.11g and Bluetooth). After amplification and mixing, the signal is filtered and

combined prior to being sampled by an ADC.

The digital receiver implements a coherent demodulator to generate a chip stream for the hardware-based

MAC. In addition, the digital receiver contains the analog radio calibration routines and control of the gain

within the receiver path.

The radio transmitter utilizes an efficient architecture in which the data stream directly modulates the VCO.

An integrated PA boosts the output power. The calibration of the TX path as well as the output power is

controlled by digital logic. If the EM260 is to be used with an external PA, the TX_ACTIVE signal should be used

to control the timing of the external switching logic.

The integrated 4.8 GHz VCO and loop filter minimize off-chip circuitry. Only a 24MHz crystal with its loading

capacitors is required to properly establish the PLL reference signal.

Always

powered

PacketTrace

ADC

RF_P,N

Integrated Flash and RAM

SIF_MISO

HF OSC

SIF

Internal

RC-OSC

IO Controller

Chip

manager

Regulator

Bias

Interrupt

Controller

RF_TX_ALT_P,N

OSCA

OSCB

SIF_MOSI

SIF_CLK

nSIF_LOAD

Encryption acclerator

Network

Processor

(XAP2b)

VREG_OUT

Watchdog

PA select

LNA

DAC

MAC

Baseband

TX_ACTIVE

Sleep

timer

BIAS_R

POR

Network Processor

Peripherals

Serial

Controller

SYNTH

nRESET

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