EM260-RTR datasheet(22/50 Pages) SILICONIMAGE

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EM260

120-0260-000M Rev 1.1

Page 22

SPI Protocol

The EM260 Low Level Protocol centers on the SPI interface for communication with a pair of GPIO for

handshake signaling.

The EM260 looks like a hardware peripheral.

The EM260 is the slave device and all transactions are initiated by the Host (the master).

The EM260 supports a reasonably high data rate.

5.1

Physical Interface Configuration

The EM260 supports both SPI Slave Mode 0 (clock is idle low, sample on rising edge) and SPI Slave Mode 3

(clock is idle high, sample on rising edge) at a maximum SPI clock rate of 5MHz, as illustrated in Figure 4. The

convention for the waveforms in this document is to show Mode 0.

Figure 4. SPI Transfer Format, Mode 0 and Mode 3

The nHOST_INT signal and the nWAKE signal are both active low. The Host must supply a pull-up resistor on

the nHOST_INT signal to prevent errant interruptions during undefined events such as the EM260 resetting.

The EM260 supplies an internal pull-up on the nWAKE signal to prevent errant interruptions during undefined

events such as the Host resetting.

5.2

SPI Transaction

The basic EM260 SPI transaction is half-duplex to ensure proper framing and to give the EM260 adequate

response time. The basic transaction, as shown in Figure 5, is composed of three sections: Command, Wait,

and Response. The transaction can be considered analogous to a function call. The Command section is the

function call, and the Response section is the return value.

Figure 5. General Timing Diagram for a SPI Transaction

MSB

LSB

MSB

LSB

EM260 – Slave (MISO)

Host – Master (MOSI)

Clock, Mode 3 (SCLK)

Clock, Mode 0 (SCLK)

nSSEL

MISO

MOSI

SCLK

nHOST_INT

Command

Response

Wait

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