MPC8360CVVALFGA datasheet(18/102 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

QUICC Engine Block Operating Frequency Limitations

5.3

QUICC Engine Block Operating Frequency Limitations

This section specify the limits of the AC electrical characteristics for the operation of the QUICC Engine block’s

communication interfaces.

NOTE

The settings listed below are required for correct hardware interface operation. Each

protocol by itself requires a minimal QUICC Engine block operating frequency setting for

meeting the performance target. Because the performance is a complex function of all the

QUICC Engine block settings, the user should make use of the QUICC Engine block

performance utility tool provided by Freescale to validate their system.

This table lists the maximal QUICC Engine block I/O frequencies and the minimal QUICC Engine block core frequency for

each interface.

DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR and DDR2 SDRAM interface of the

MPC8360E/58E.

Table 13. QUICC Engine Block Operating Frequency Limitations

Interface

Interface Operating

Frequency (MHz)

Max Interface Bit

Rate (Mbps)

Min QUICC Engine

Operating

Frequency1 (MHz)

Notes

Ethernet Management: MDC/MDIO

10 (max)

—

MII

25 (typ)

100

—

RMII

50 (typ)

100

—

GMII/RGMII/TBI/RTBI

125 (typ)

1000

250

—

SPI (master/slave)

10 (max)

—

UCC through TDM

50 (max)

× F

MCC

25 (max)

16.67

× F

2, 4

UTOPIA L2

50 (max)

800

× F

POS-PHY L2

50 (max)

800

× F

HDLC bus

10 (max)

—

HDLC/transparent

50 (max)

8/3

× F

2, 3

UART/async HDLC

3.68 (max internal ref

clock)

115 (Kbps)

—

BISYNC

2 (max)

—

USB

48 (ref clock)

—

Notes:

1. The QUICC Engine module needs to run at a frequency higher than or equal to what is listed in this table.

2. ‘F’ is the actual interface operating frequency.\

3. The bit rate limit is independent of the data bus width (that is, the same for serial, nibble, or octal interfaces).

4. TDM in high-speed mode for serial data interface.

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