MPC8360CVVALFGA datasheet(90/102 Pages) FREESCALE

90 / 102 page

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

Suggested PLL Configurations

The following steps describe how to use above table. See Example 1.

Choose the up or down sections in the table according to input clock rate 33 MHz or 66 MHz.

Select a suitable CSB and core clock rates from Table 76. Copy the SPMF and CORE PLL configuration bits.

Select a suitable QUICC Engine block clock rate from Table 76. Copy the CEPMF and CEPDF configuration bits.

Insert the chosen SPMF, COREPLL, CEPMF and CEPDF to the RCWL fields, respectively.

10000

—

533

—

∞∞

10001

—

566

—

∞

66 MHz CLKIN/PCI_SYNC_IN Options

s1h

0011

0000110

200

400

—

∞∞

∞

s2h

0011

0000101

200

500

—

∞∞

s3h

0011

0000110

200

600

—

∞

s4h

0100

0000011

266

400

—

∞∞

∞

s5h

0100

0000100

266

533

—

∞∞

s6h

0100

0000101

266

667

—

∞

s7h

0101

0000010

333

—

∞∞

∞

s8h

0101

0000011

333

500

—

∞∞

s9h

0101

0000100

333

667

—

∞

c1h

00101

—

333

∞∞

∞

c2h

00110

—

400

∞∞

∞

c3h

00111

—

466

—

∞∞

c4h

01000

—

533

—

∞∞

c5h

01001

—

600

—

∞

Note:

1. The Conf No. consist of prefix, an index and a postfix. The prefix “s” and “c” stands for “syset” and “ce” respectively. The

postfix “h” stands for “high input clock.’”The index is a serial number.

Table 76. Suggested PLL Configurations (continued)

Conf

No.1

SPMF

CORE

PLL

CEPMF

CEPDF

Input

Clock Freq

(MHz)

CSB Freq

(MHz)

Core Freq

(MHz)

QUICC

Engine

Freq (MHz)

400

(MHz)

533

(MHz)

667

(MHz)

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