PIC16C72 datasheet(71/128 Pages) MICROCHIP

71 / 128 page

PIC16C72 Series

 1998-2013 Microchip Technology Inc.

Preliminary

DS39016B-page 71

10.13

Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit (STATUS<3>) is cleared, the

TO (STATUS<4>) bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had,

before the SLEEP instruction was executed (driving

high, low, or hi-impedance).

For lowest current consumption in this mode, place all

I/O pins at either VDD, or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down

the A/D, disable external clocks. Pull all I/O pins, that

are hi-impedance inputs, high or low externally to avoid

switching currents caused by floating inputs. The

T0CKI input should also be at VDD or VSS for lowest

current consumption. The contribution from on-chip

pull-ups on PORTB should be considered.

The MCLR pin must be at a logic high level (VIHMC).

10.13.1 WAKE-UP FROM SLEEP

The device can wake up from SLEEP through one of

the following events:

External reset input on MCLR pin.

Watchdog

Timer

Wake-up

(if

WDT

was

enabled).

Interrupt from INT pin, RB port change, or some

Peripheral Interrupts.

External MCLR Reset will cause a device reset. All

other events are considered a continuation of program

execution and cause a "wake-up". The TO and PD bits

in the STATUS register can be used to determine the

cause of device reset. The PD bit, which is set on

power-up, is cleared when SLEEP is invoked. The TO

bit is cleared if a WDT time-out occurred (and caused

wake-up).

The following peripheral interrupts can wake the device

from SLEEP:

TMR1 interrupt.

Timer1 must be operating as

an asynchronous counter.

SSP (Start/Stop) bit detect interrupt.

SSP transmit or receive in slave mode (SPI/I2C).

CCP capture mode interrupt.

A/D conversion (when A/D clock source is RC).

Special event trigger (Timer1 in asynchronous

mode using an external clock).

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