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PIC16C72 Folha de dados(PDF) 56 Page - Microchip Technology

Nome de Peças PIC16C72
Descrição Electrónicos  8-Bit CMOS Microcontrollers with A/D Converter
PDF  128 Pages
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Fabricante Electrônico  MICROCHIP [Microchip Technology]
Página de início  http://www.microchip.com
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PIC16C72 Series
DS39016B-page 56
Preliminary
 1998-2013 Microchip Technology Inc.
9.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 9-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the ana-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is 10
k
. After the analog input channel is selected
(changed) this acquisition must be done before the
conversion can be started.
To calculate the minimum acquisition time, TACQ, see
the
PIC®
Mid-Range
MCU
Reference
Manual,
DS33023. This equation calculates the acquisition time
to within 1/2 LSb error (512 steps for the A/D). The 1/2
LSb error is the maximum error allowed for the A/D to
meet its specified accuracy.
FIGURE 9-4:
ANALOG INPUT MODEL
CPIN
VA
Rs
ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V
I leakage
RIC
 1k
Sampling
Switch
SS
RSS
CHOLD
= DAC capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
567 8 9 10 11
( k
 )
VDD
= 51.2 pF
 500 nA
Legend CPIN
VT
I leakage
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions



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