PIC16C72 datasheet(5/128 Pages) MICROCHIP

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PIC16C72 Series

 1998-2013 Microchip Technology Inc.

Preliminary

DS39016B-page 5

2.0

MEMORY ORGANIZATION

There are two memory blocks in PIC16C72 Series

devices. These are the program memory and the data

memory. Each block has its own bus, so that access to

both blocks can occur during the same oscillator cycle.

The data memory can further be broken down into the

general purpose RAM and the Special Function

Registers (SFRs). The operation of the SFRs that

control the “core” are described here. The SFRs used

to control the peripheral modules are described in the

section discussing each individual peripheral module.

Additional information on device memory may be found

in the PIC® Mid-Range Reference Manual, DS33023.

2.1

Program Memory Organization

PIC16C72 Series devices have a 13-bit program coun-

ter capable of addressing a 2K x 14 program memory

space. The address range for this program memory is

0000h - 07FFh. Accessing a location above the physi-

cally implemented address will cause a wraparound.

The reset vector is at 0000h and the interrupt vector is

at 0004h.

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK

PC<12:0>

0000h

0004h

0005h

07FFh

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

0800h

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