PIC16C72 datasheet(68/128 Pages) MICROCHIP

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PIC16C72 Series

DS39016B-page 68

Preliminary

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10.10

Interrupts

The PIC16C72/CR72 has 8 sources of interrupt. The

interrupt control register (INTCON) records individual

interrupt requests in flag bits. It also has individual and

global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. When bit GIE is enabled, and an

interrupt’s flag bit and mask bit are set, the interrupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous

registers.

Individual

interrupt

bits

are

set

regardless of the status of the GIE bit. The GIE bit is

cleared on reset.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine as well as sets the GIE bit, which

re-enables interrupts.

The RB0/INT pin interrupt, the RB port change interrupt

and the TMR0 overflow interrupt flags are contained in

the INTCON register.

The peripheral interrupt flags are contained in the spe-

cial function registers PIR1 and PIR2. The correspond-

ing interrupt enable bits are contained in special

function registers PIE1 and PIE2, and the peripheral

interrupt enable bit is contained in special function reg-

ister INTCON.

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs. The latency

is the same for one or two cycle instructions. Individual

interrupt flag bits are set regardless of the status of

their corresponding mask bit or the GIE bit

10.10.1 INT INTERRUPT

External interrupt on RB0/INT pin is edge triggered:

either rising if bit INTEDG (OPTION<6>) is set, or fall-

ing, if the INTEDG bit is clear. When a valid edge

appears

the

RB0/INT

pin,

flag

bit

INTF

(INTCON<1>) is set. This interrupt can be disabled by

clearing enable bit INTE (INTCON<4>). Flag bit INTF

must be cleared in software in the interrupt service rou-

tine before re-enabling this interrupt. The INT interrupt

can wake-up the processor from SLEEP, if bit INTE was

set prior to going into SLEEP. The status of global inter-

rupt enable bit GIE decides whether or not the proces-

sor branches to the interrupt vector following wake-up.

See Section 10.13 for details on SLEEP mode.

10.10.2 TMR0 INTERRUPT

An overflow (FFh

 00h) in the TMR0 register will set

flag bit T0IF (INTCON<2>). The interrupt can be

enabled/disabled by setting/clearing enable bit T0IE

(INTCON<5>). (Section 4.0)

10.10.3 PORTB INTCON CHANGE

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit RBIE (INTCON<4>).

(Section 3.2)

FIGURE 10-11: INTERRUPT LOGIC

Note:

Individual interrupt flag bits are set regard-

less of the status of their corresponding

mask bit or the GIE bit.

ADIF

ADIE

SSPIF

SSPIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

T0IF

T0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake-up (If in SLEEP mode)

Interrupt to CPU

Clear GIE bit

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