PIC16F5X datasheet(40/88 Pages) MICROCHIP

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PIC16F5X

DS41213D-page 38

8.2

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator which does not require any external

components. This RC oscillator is separate from the

RC oscillator of the OSC1/CLKIN pin. That means that

the WDT will run even if the clock on the OSC1/CLKIN

and OSC2/CLKOUT pins have been stopped, for

example, by execution of a SLEEP instruction. During

normal operation or Sleep, a WDT Reset or Wake-up

Reset generates a device Reset.

The TO bit (STATUS<4>) will be cleared upon a

Watchdog

Timer

Reset

(Section 3.3

“STATUS

The WDT can be permanently disabled by program-

ming the Configuration bit WDTE as a ‘0’ (Section 8.1

“Configuration Bits”). Refer to the PIC16F54 and

PIC16F57 Programming Specifications to determine

how to access the Configuration Word. These

documents can be found on the Microchip web site at

www.microchip.com.

8.2.1

WDT PERIOD

An 8-bit counter is available as a prescaler for the

Timer0 module (Section 7.2 “Prescaler”), or as a

postscaler for the Watchdog Timer (WDT), respec-

tively. For simplicity, this counter is being referred to as

“prescaler” throughout this data sheet.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio (Section 3.4

“Option Register”).

The WDT has a nominal time-out period of 18 ms (with

no prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT (under software control) by writ-

ing to the Option register. Thus time-out, a period of a

nominal 2.3 seconds, can be realized. These periods

vary with temperature, VDD and part-to-part process

variations (see Device Characterization).

Under worst case conditions (VDD = Min., Temperature

= Max., WDT prescaler = 1:128), it may take several

seconds before a WDT time-out occurs.

8.2.2

WDT PROGRAMMING

CONSIDERATIONS

The CLRWDT instruction clears the WDT and the

prescaler, if assigned to the WDT, and prevents it from

timing out and generating a device Reset.

The SLEEP instruction resets the WDT and the

prescaler, if assigned to the WDT. This gives the

maximum Sleep time before a WDT Wake-up Reset.

FIGURE 8-1:

WATCHDOG TIMER

BLOCK DIAGRAM

TABLE 8-1:

SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Note:

The prescaler may be used by either the

Timer0 module or the WDT, but not both.

Thus, a prescaler assignment for the

Timer0 module means that there is no

prescaler for the WDT, and vice-versa.

Note

T0CS, T0SE, PSA, PS<2:0> are bits in the

Option register.

Prescaler

Watchdog

Timer

WDTE

PSA(1)

8-to-1

MUX

To TMR0

MUX

PSA(1)

WDT Time-out

From TMR0 Clock Source

PS<2:0>(1)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-on

Reset

Value on

MCLR and

WDT Reset

N/A

OPTION

—

T0CS

T0SE

PSA

PS2

PS1

PS0

--11 1111 --11 1111

Legend: Shaded cells not used by Watchdog Timer, - = unimplemented, read as ‘0’, u = unchanged

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