SH7014 datasheet(24/754 Pages) RENESAS

24 / 754 page

Rev.5.00 Sep. 27, 2007 Page xxiv of xxxiv

REJ09B0398-0500

8.2.3

Wait Control Register 1 (WCR1)......................................................................... 112

8.2.4

Wait Control Register 2 (WCR2)......................................................................... 114

8.2.5

DRAM Area Control Register (DCR) ................................................................. 115

8.2.6

Refresh Timer Control/Status Register (RTCSR) ................................................ 118

8.2.7

Refresh Timer Counter (RTCNT)........................................................................ 121

8.2.8

Refresh Time Constant Register (RTCOR) ......................................................... 122

8.3

Accessing Ordinary Space ................................................................................................ 123

8.3.1

Basic Timing........................................................................................................ 123

8.3.2

Wait State Control ............................................................................................... 124

8.3.3

CS Assert Period Extension................................................................................. 126

8.4

DRAM Access .................................................................................................................. 127

8.4.1

DRAM Direct Connection ................................................................................... 127

8.4.2

Basic Timing........................................................................................................ 128

8.4.3

Wait State Control ............................................................................................... 129

8.4.4

Burst Operation.................................................................................................... 133

8.4.5

Refresh Timing .................................................................................................... 135

8.5

Address/Data Multiplex I/O Space Access ....................................................................... 136

8.5.1

Basic Timing........................................................................................................ 136

8.5.2

Wait State Control ............................................................................................... 138

8.5.3

CS Assertion Extension ....................................................................................... 139

8.6

Waits between Access Cycles ........................................................................................... 140

8.6.1

Prevention of Data Bus Conflicts......................................................................... 140

8.6.2

Simplification of Bus Cycle Start Detection ........................................................ 142

8.7

Bus Arbitration.................................................................................................................. 143

8.8

Memory Connection Examples......................................................................................... 143

8.9

On-chip Peripheral I/O Register Access ........................................................................... 145

8.10

CPU Operation when Program Is in External Memory .................................................... 146

Section 9 Direct Memory Access Controller (DMAC) ............................................ 147

9.1

Overview........................................................................................................................... 147

9.1.1

Features................................................................................................................ 147

9.1.2

Block Diagram..................................................................................................... 148

9.1.3

Pin Configuration................................................................................................. 149

9.1.4

9.2

Register Descriptions ........................................................................................................ 151

9.2.1

DMA Source Address Registers 0, 1 (SAR0, SAR1) .......................................... 151

9.2.2

DMA Destination Address Registers 0, 1 (DAR0, DAR1).................................. 152

9.2.3

DMA Transfer Count Registers 0, 1 (DMATCR0, DMATCR1)......................... 153

9.2.4

DMA Channel Control Registers 0, 1 (CHCR0, CHCR1)................................... 154

9.2.5

DMAC Operation Register (DMAOR) ................................................................ 159

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