SH7014 datasheet(49/754 Pages) RENESAS

49 / 754 page

1. SH7014/16/17 Overview

Rev.5.00 Sep. 27, 2007 Page 15 of 716

REJ09B0398-0500

Classification

Symbol

I/O

Name

Function

Data bus

D0 to D15

I/O

Data bus

16-bit bidirectional data bus

Bus control

CS0 to CS3 O

Chip selects 0 to

Chip select signals for external

memory or devices.

Read

Indicates reading from an external

device.

WRH

Upper write

Indicates writing the upper 8 bits of

external data.

WRL

Lower write

Indicates writing the lower 8 bits of

external data.

WAIT

Wait

Input causes insertion of wait cycles

into the bus cycle during external

space access.

RAS

Row address

strobe

Timing signal for DRAM row address

strobe.

CASH

Upper column

address strobe

Timing signal for DRAM column

address strobe.

Output when the upper 8 bits of data

are accessed.

CASL

Lower column

address strobe

Timing signal for DRAM column

address strobe.

Output when the lower 8 bits of data

are accessed.

RDWR

DRAM read/write

DRAM write strobe signal.

Address hold

Address hold timing signal for

devices using an address/data

multiplex bus.

Multifunction

Timer Pulse Unit

(MTU)

TCLKA

TCLKB

TCLKC

TCLKD

MTU timer clock

input

Input pins for external clocks to the

MTU counter.

TIOC0A

TIOC0B

TIOC0C

TIOC0D

I/O

MTU input

capture/output

compare

(channel 0)

Channel 0 input capture input/output

compare output/PWM output pins.

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