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HD64F2149YV Folha de dados(PDF) 960 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 960 Page - Renesas Technology Corp |
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960 / 1075 page ![]() Appendix B Internal I/O Registers Rev. 3.00 Jan 18, 2006 page 932 of 1044 REJ09B0280-0300 SMR1—Serial Mode Register 1 H'FF88 SCI1 SMR2—Serial Mode Register 2 H'FFA0 SCI2 SMR0—Serial Mode Register 0 H'FFD8 SCI0 7 C/ A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/ E 0 R/W 3 STOP 0 R/W 0 CKS0 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W Bit Initial value Read/Write Clock select 1 and 0 0 φ clock φ/4 clock φ/16 clock φ/64 clock 0 1 10 1 Stop bit length 0 1 stop bit 2 stop bits 1 Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Parity mode 0 Even parity Odd parity 1 Parity enable 0 Parity bit addition and checking disabled Parity bit addition and checking enabled 1 Character length 0 8-bit data 7-bit data* 1 Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Also, LSB-first/ MSB-first selection is not available. Communication mode 0 Asynchronous mode Synchronous mode 1 |
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