HD64F2149YV datasheet(963/1075 Pages) RENESAS

963 / 1075 page

Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 935 of 1044

REJ09B0280-0300

ICSR1—I

2C Bus Status Register 1

H'FF89

IIC1

ICSR0—I

2C Bus Status Register 0

H'FFD9

IIC0

ESTP

R/(W)*1

STOP

R/(W)*1

IRTR

R/(W)*1

AASX

R/(W)*1

ACKB

R/W

AAS

R/(W)*1

ADZ

R/(W)*1

Bit

Initial value

Read/Write

Acknowledge bit

Receive mode: 0 is output at

acknowledge output timing

Transmit mode: indicates that

the receiving device has

acknowledged the data (signal is 0)

Receive mode: 1 is output at

acknowledge output timing

Transmit mode: indicates that

the receiving device has not

acknowledged the data (signal is 1)

Notes:

General call address recognition flag*2

General call address not recognized

General call address recognized

Slave address recognition flag*2

Slave address or general call address

not recognized

Slave address or general call address

recognized

Arbitration lost*2

Bus arbitration won

Arbitration lost

Second slave address recognition flag*2

Second slave address not recognized

Second slave address recognized

I2C bus interface continuous transmission/reception interrupt request flag*2

Waiting for transfer, or transfer in progress

Continuous transfer state

Normal stop condition detection flag*2

No normal stop condition

1In I2C bus format slave mode: Normal stop condition detected

In other modes: No meaning

Error stop condition detection flag*2

No error stop condition

1In I2C bus format slave mode: Error stop condition detected

In other modes: No meaning

1. Only 0 can be written, to clear the flag.

2. For the clearing and setting conditions, see section 16.2.6, I2C Bus Status Register (ICSR).

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