HD64F2149YV datasheet(964/1075 Pages) RENESAS

964 / 1075 page

Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 936 of 1044

REJ09B0280-0300

SCR1—Serial Control Register 1

H'FF8A

SCI1

SCR2—Serial Control Register 2

H'FFA2

SCI2

SCR0—Serial Control Register 0

H'FFDA

SCI0

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

Read/Write

Clock enable 1 and 0

Asynchronous

mode

Synchronous

mode

Asynchronous

mode

Synchronous

mode

Asynchronous

mode

Synchronous

mode

Asynchronous

mode

Synchronous

mode

Internal clock/SCK pin

functions as I/O port

Internal clock/SCK pin

functions as serial clock output

Internal clock/SCK pin

functions as clock output

Internal clock/SCK pin

functions as serial clock output

External clock/SCK pin

functions as clock input

External clock/SCK pin

functions as serial clock input

External clock/SCK pin

functions as clock input

External clock/SCK pin

functions as serial clock input

Transmit end interrupt enable

Transmit-end interrupt (TEI) request disabled

Transmit-end interrupt (TEI) request enabled

Multiprocessor interrupt enable

Multiprocessor interrupts disabled (normal reception mode)

[Clearing conditions]

• When the MPIE bit is cleared to 0

• When data with MPB = 1 is received

Multiprocessor interrupts enabled

Receive interrupt (RXI) requests, receive-error interrupt (ERI)

requests, and setting of the RDRF, FER, and ORER flags in

SSR are disabled until data with the multiprocessor bit set to

1 is received

Receive enable

Reception disabled

Reception enabled

Transmit enable

Transmission disabled

Transmission enabled

Receive interrupt enable

Receive-data-full interrupt (RXI)

request and receive-error interrupt

(ERI) request disabled

Receive-data-full interrupt (RXI)

request and receive-error interrupt

(ERI) request enabled

Transmit interrupt enable

Transmit-data-empty interrupt

(TXI) request disabled

Transmit-data-empty interrupt

(TXI) request enabled

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