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HD64F2149YV Folha de dados(PDF) 944 Page - Renesas Technology Corp

Nome de Peças HD64F2149YV
Descrição Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV Folha de dados(HTML) 944 Page - Renesas Technology Corp

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Appendix B Internal I/O Registers
Rev. 3.00 Jan 18, 2006 page 916 of 1044
REJ09B0280-0300
DDCSWR—DDC Switch Register
H'FEE6
IIC0
7
SWE
0
R/W
6
SW
0
R/W
5
IE
0
R/W
4
IF
0
R/(W)*1
3
CLR3
1
W*2
0
CLR0
1
W*2
2
CLR2
1
W*2
1
CLR1
1
W*2
Bit
Initial value
Read/Write
DDC mode switch interrupt flag
0
No interrupt is requested when automatic format switching
is executed
[Clearing condition]
When 0 is written in IF after reading IF = 1
1
An interrupt is requested when automatic format switching
is executed
[Setting condition]
When a falling edge is detected on the SCL
pin when SWE = 1
DDC mode switch interrupt enable bit
0
Interrupt when automatic format switching is executed is disabled
1
Interrupt when automatic format switching is executed is enabled
DDC mode switch
0
IIC channel 0 is used with the I2C bus format
[Clearing conditions]
• When 0 is written by software
• When a falling edge is detected on the SCL pin when SWE = 1
1
IIC channel 0 is used in formatless mode
[Setting condition]
When 1 is written in SW after reading SW = 0
DDC mode switch enable
0
Automatic switching of IIC channel 0 from formatless mode to I2C bus format is disabled
1
Automatic switching of IIC channel 0 from formatless mode to I2C bus format is enabled
IIC clear bits
Bit 3
CLR3
0
1
Description
Setting prohibited
Setting prohibited
IIC0 internal latch cleared
IIC1 internal latch cleared
IIC0 and IIC1 internal latches cleared
Invalid setting
Bit 2
CLR2
0
1
—
Bit 1
CLR1
—
0
1
—
Bit 0
CLR0
—
0
1
0
1
—
Notes: 1. Only 0 can be written, to clear the flag.
2. Always read as 1.



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