HD64F2149YV datasheet(940/1075 Pages) RENESAS

940 / 1075 page

Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 912 of 1044

REJ09B0280-0300

KBCRH0—Keyboard Control Register H0

H'FED8

Keyboard Buffer Controller

KBCRH1—Keyboard Control Register H1

H'FEDC

Keyboard Buffer Controller

KBCRH2—Keyboard Control Register H2

H'FEE0

Keyboard Buffer Controller

KBIOE

KBF

PER

KBS

KCLKI

KDI

KBFSEL

KBIE

Bit

Initial value

Read/Write

654

111

R/W

R/(W)*

R/W

Keyboard stop

0 “0” stop bit received

1 “1” stop bit received

Note: * Only 0 can be written, to clear the flag.

Parity error

0 [Clearing condition]

Read PER when PER =1,

then write 0 in PER

1 [Setting condition]

When an odd parity error occurs

Keyboard buffer register full

0 [Clearing condition]

Read KBF when KBF =1, then write 0 in KBF

Keyboard interrupt enable

0 Interrupt requests are disabled

1 Interrupt requests are enabled

Keyboard buffer register full select

0 KBF bit is used as KCLK fall interrupt flag

1 KBF bit is used as keyboard buffer register full flag

Keyboard data in

0 KD I/O pin is low

1 KD I/O pin is high

Keyboard clock in

0 KCLK I/O pin is low

1 KCLK I/O pin is high

Keyboard in/out enable

0 The keyboard buffer controller is non-operational (KCLK and KD signal pins

have port functions)

1 The keyboard buffer controller is enabled for transmission and reception

(KCLK and KD signal pins are in the bus drive state)

[Setting conditions]

• When data has been received normally while

KBFSEL = 1, and has been transferred to

KBBR (keyboard buffer register full flag)

• When a KCLK falling edge has been detected

while KBFSEL = 0 (KCLK interrupt flag)

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