HD64F2149YV datasheet(948/1075 Pages) RENESAS

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Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 920 of 1044

REJ09B0280-0300

DTCER—DTC Enable Register

H'FEEE to H'FEF2

DTC

DTCE7

R/W

DTCE6

R/W

DTCE5

R/W

DTCE4

R/W

DTCE3

R/W

DTCE0

R/W

DTCE2

R/W

DTCE1

R/W

Bit

Initial value

Read/Write

DTC activation enable

DTC activation by interrupt is disabled

[Clearing conditions]

• When data transfer ends with the DISEL bit set to 1

• When the specified number of transfers end

DTC activation by interrupt is enabled

[Holding condition]

When the DISEL bit is 0 and the specified number of transfers

have not ended

DTVECR—DTC Vector Register

H'FEF3

DTC

SWDTE

R/(W)*

DTVEC6

R/W

DTVEC5

R/W

DTVEC4

R/W

DTVEC3

R/W

DTVEC0

R/W

DTVEC2

R/W

DTVEC1

R/W

Bit

Initial value

Read/Write

Note: *

Sets vector number for DTC software activation

DTC software activation enable

DTC software activation is disabled

[Clearing condition]

When the DISEL bit is 0 and the specified number of transfers have

not ended

DTC software activation is enabled

[Holding conditions]

• When data transfer ends with the DISEL bit set to 1

• When the specified number of transfers end

• During software-activated deta transfer

A value of 1 can always be written to the SWDTE bit, but 0 can only be written

after 1 is read.

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