HD64F2149YV datasheet(946/1075 Pages) RENESAS

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Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 918 of 1044

REJ09B0280-0300

ISR—IRQ Status Register

H'FEEB

Interrupt Controller

IRQ7F

R/(W)*1

IRQ6F

R/(W)*1

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ0F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

Bit

Initial value

Read/Write

IRQ7 to IRQ0 flags

[Clearing conditions]

• Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF

• When interrupt exception handling is executed while low-level detection

is set (IRQnSCB = IRQnSCA = 0) and

IRQn input is high*2

• When IRQn interrupt exception handling is executed while falling, rising,

or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)*2

[Setting conditions]

• When

IRQn input goes low when low-level detection is set

(IRQnSCB = IRQnSCA = 0)

• When a falling edge occurs in

IRQn input while falling edge detection is

set (IRQnSCB = 0, IRQnSCA = 1)

• When a rising edge occurs in

IRQn input while rising edge detection is

set (IRQnSCB = 1, IRQnSCA = 0)

• When a falling or rising edge occurs in

IRQn input while both-edge

detection is set (IRQnSCB = IRQnSCA = 1)

Notes: 1. Only 0 can be written, to clear the flag.

(n = 7 to 0)

2. When a product, in which a DTC is incorporated, is used in the following settings,

the corresponding flag bit is not automatically cleared even when exception handing,

which is a clear condition, is executed and the bit is held at 1.

(1) When DTCEA3 is set to 1 (ADI is set to an interrupt source), IRQ4F flag is not

automatically cleared.

(2) When DTCEA2 is set to 1 (ICIA is set to an interrupt source), IRQ5F flag is not

automatically cleared.

(3) When DTCEA1 is set to 1 (ICIB is set to an interrupt source), IRQ6F flag is not

automatically cleared.

(4) When DTCEA0 is set to 1 (OCIA is set to an interrupt source), IRQ7F flag is not

automatically cleared.

When activation interrupt sources of DTC and IRQ interrupts are used with the above

combinations, clear the interrupt flag by software in the interrupt handling routine of

the corresponding IRQ.

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