HD64F2149YV datasheet(783/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Fabricante Electrônico	RENESAS [Renesas Technology Corp]

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Section 24 Power-Down State

Rev. 3.00 Jan 18, 2006 page 755 of 1044

REJ09B0280-0300

Bit 5

NESEL

Description

Sampling at

φ divided by 32

(Initial value)

Sampling at

φ divided by 4

Bit 4—Subclock Input Enable (EXCLE): Controls subclock input from the EXCL pin.

Bit 4

EXCLE

Description

Subclock input from EXCL pin is disabled

(Initial value)

Subclock input from EXCL pin is enabled

Bit 3 (H8S/2149)—Reserved: These bits cannot be modified and are always read as 0.

Bit 3 (H8S/2169)—Reserved: Do not write 1 to this bit.

Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0.

24.2.3

Timer Control/Status Register (TCSR)

TCSR1

OVF

R/(W)*

WT/

R/W

TME

R/W

PSS

R/W

RST/

NMI

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Note: * Only 0 can be written in bit 7, to clear the flag.

TCSR1 is an 8-bit readable/writable register that performs selection of the WDT1 TCNT input

clock, mode, etc.

Only bit 4 is described here. For details of the other bits, see section 14.2.2, Timer Control/Status

TCSR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

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