HD64F2149YV datasheet(781/1075 Pages) RENESAS

781 / 1075 page

Section 24 Power-Down State

Rev. 3.00 Jan 18, 2006 page 753 of 1044

REJ09B0280-0300

Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus

master in high-speed mode and medium-speed mode. When operating the device after a transition

to subactive mode or watch mode, bits SCK2 to SCK0 should all be cleared to 0.

Bit 2

Bit 1

Bit 0

SCK2

SCK1

SCK0

Description

Bus master is in high-speed mode

(Initial value)

Medium-speed clock is

φ/2

Medium-speed clock is

φ/4

Medium-speed clock is

φ/8

Medium-speed clock is

φ/16

Medium-speed clock is

φ/32

——

24.2.2

Low-Power Control Register (LPWRCR)

DTON

R/W

LSON

R/W

NESEL

R/W

EXCLE

R/W

—

Bit

Initial value

Read/Write

LPWRCR is an 8-bit readable/writable register that performs power-down mode control.

LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Direct-Transfer On Flag (DTON): Specifies whether a direct transition is made between

high-speed mode, medium-speed mode, and subactive mode when making a power-down

transition by executing a SLEEP instruction. The operating mode to which the transition is made

after SLEEP instruction execution is determined by a combination of other control bits.

HD64F2149YV Folha de dados(PDF) 781 Page - Renesas Technology Corp

HD64F2149YV Folha de dados(HTML) 781 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL